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參數(shù)資料
| 型號： | UPD784218YGC |
| 廠商： | NEC Corp. |
| 英文描述： | Cable; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No |
| 中文描述： | 16-/8-bit的單晶片微控制器 |
| 文件頁數(shù)： | 42/92頁 |
| 文件大?。?/td> | 617K |
| 代理商： | UPD784218YGC |
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μ
PD784218, 784218Y
Data Sheet U12304EJ2V0DS00
42
8.7.2 Clocked serial interface (CSI)
In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in
synchronization with this clock.
(1) 3-wire serial I/O mode
This mode is to communicate with devices having the conventional clocked serial interface.
Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial
data (SI0 and SO0) lines.
Generally, a handshake line is necessary to check the reception status.
Figure 8-12. Block Diagram When in 3-Wire Serial I/O Mode
SI0
SO0
SCK0
INTCSI0
TO2
f
XX
/8
f
XX
/16
Internal bus
Interrupt
generator
Selector
Serial clock
counter
Serial clock
controller
Serial I/O shift register 0
(SIO0)
8
(2) I
2
C bus (Inter IC) bus mode (multi-master supporting)
This mode is for communication with devices conforming to the I
2
C bus format.
This mode is for transferring 8-bit data between two or more devices by using two lines: a serial clock (SCL0)
and a serial data bus (SDA0).
During transfer, a "start condition", "data", and "stop condition" can be output onto the serial data bus. During
reception, this data is automatically detected by hardware.
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| UPD784218GC | Connector assemblies, Network cables; |
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| UPD784218 | 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD784218GC-XXX-8EU | 16-Bit Microcontroller |
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