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參數(shù)資料
| 型號： | UPD784218YGC |
| 廠商： | NEC Corp. |
| 英文描述： | Cable; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No |
| 中文描述： | 16-/8-bit的單晶片微控制器 |
| 文件頁數(shù)： | 65/92頁 |
| 文件大?。?/td> | 617K |
| 代理商： | UPD784218YGC |
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μ
PD784218, 784218Y
Data Sheet U12304EJ2V0DS00
65
Subsystem Clock Oscillator Characteristics (T
A
= –40 to +85
°
C)
Resonator Recommended Circuit
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Crystal
resonator
Oscillation
frequency (f
XT
)
32
32.768
35
kHz
Oscillation
stabilization time
Note
4.5 V
≤
V
DD
≤
5.5 V
1.2
2
s
2.2 V
≤
V
DD
< 4.5 V
10
External
clock
XT1 input
frequency (f
XT
)
32
35
kHz
XT1 input high-/low-
level width (t
XTH
, t
XTL
)
5
15
μ
s
Note
Time required to stabilize oscillation after the power supply voltage (V
DD
) is applied.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V
SS
.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark
For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
V
SS
XT2
XT1
XT2
XT1
PD74HCU04
μ
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