參數(shù)資料
型號(hào)： UPD784218YGC
廠商： NEC Corp.
英文描述： Cable; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No
中文描述： 16-/8-bit的單晶片微控制器
文件頁數(shù)： 46/92頁
文件大?。?/td> 617K
代理商： UPD784218YGC
μ
PD784218, 784218Y
Data Sheet U12304EJ2V0DS00
46
9. INTERRUPT FUNCTION
The three types of servicing in response to an interrupt request shown in Table 9-1 can be selected by program.
Table 9-1. Servicing of Interrupt Request
Servicing Mode
Servicing Means
Servicing
Contents of PC and PSW
Vectored interrupt
Software
Branches and executes servicing routine
(servicing is arbitrary)
Saves to and restores
from stack
Context switching
Automatically switches register bank,
branches and executes servicing routine
(servicing is arbitrary)
Saves to or restores from
fixed area in register bank
Macro service
Firmware
Executes data transfer between memory
and I/O (servicing is fixed)
Retained
9.1 Interrupt Sources
Table 9-2 shows the interrupt sources available. As shown, interrupts are generated by 29 sources, execution
of the BRK instruction, BRKCS instruction, or an operand error.
The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt
servicing, and so that which of the two or more interrupts that simultaneously occur should be serviced first can be
decided. When the macro service function is used, however, nesting always proceeds (i.e., is not held pending).
The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having
the same priority, are simultaneously generated (refer to
Table 9-2
).
Table 9-2. Interrupt Sources (1/2)
Type
Default
Priority
Source
Internal/
External
Macro
Service
Name
Trigger
Software
—
BRK instruction
BRKCS instruction
Instruction execution
Instruction execution
—
—
Operand error
If result of exclusive OR between operands
byte and byte is not FFH when MOV STBC,
#byte instruction, MOV WDM, #byte instruction,
or LOCATION instruction is executed
Non-maskable
—
NMI
Pin input edge detection
External
—
INTWDT
INTWDTM
Overflow of watchdog timer
Overflow of watchdog timer
Internal
Internal
Maskable
0 (
highest
)
√
1
INTP0
Pin input edge detection
External
2
3
INTP1
INTP2
4
5
INTP3
INTP4
6
INTP5
7
8
INTP6
INTIIC0
End of I
2
C bus transfer by CSI0
Internal
INTCSI0
End of 3-wire transfer by CSI0
9
INTSER1
Occurrence of UART reception error in ASI1
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