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參數(shù)資料
| 型號(hào)： | UPD78011HGK-XXX-8A8 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 12 X 12 MM, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 53/70頁(yè) |
| 文件大?。?/td> | 540K |
| 代理商： | UPD78011HGK-XXX-8A8 |
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55
PD78011H, 78012H, 78013H, 78014H
Data Retention Timing (STOP Mode Release by RESET)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Resolution
8
bit
Overall error Note
2.7 V
≤ AVREF ≤ AVDD
0.6
%
1.8 V
≤ AVREF ≤ 2.7 V
1.4
%
Conversion time
tCONV
2.0 V
≤ AVDD < 5.5 V
19.1
200
s
1.8 V
≤ AVDD < 2.0 V
38.2
200
s
Sampling time
tSAMP
24/fX
s
Analog input voltage
VIAN
AVSS
AVREF
V
Reference voltage
AVREF
1.8
AVDD
V
AVREF–AVSS resistance
RAIREF
414
k
A/D converter characteristics (TA = –40 to +85
°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Note Overall error excluding quantization error (
±1/2 LSB). It is indicated as a ratio to the full-scale value.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85
°C)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Data retention supply
VDDDR
1.8
5.5
V
voltage
Data retention supply
IDDDR
VDDDR = 1.8 V
0.1
10
A
current
Subsystem clock stop and feed-
back resister disconnected
Release signal set time
tSREL
0
s
Oscillation stabilization
tWAIT
Release by RESET
218/fX
ms
wait time
Release by interrupt
Note
ms
Note In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 213/
fX and 215/fX to 218/fX is possible.
VDD
STOP Instruction Execution
RESET
VDDDR
Internal Reset Operation
HALT Mode
Operating Mode
tWAIT
tSREL
Data Retension Mode
STOP Mode
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