參數(shù)資料
型號： UPD78011HGK-XXX-8A8
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, PLASTIC, LQFP-64
文件頁數(shù)： 39/70頁
文件大小： 540K
代理商： UPD78011HGK-XXX-8A8
42
PD78011H, 78012H, 78013H, 78014H
(ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY2
4.5 V
≤ VDD ≤ 5.5 V
800
ns
2.7 V
≤ VDD < 4.5 V
1600
ns
2.0 V
≤ VDD < 2.7 V
3200
ns
4800
ns
SCK0 high/low-level
tKH2
4.5 V
≤ VDD ≤ 5.5 V
400
ns
width
tKL2
2.7 V
≤ VDD < 4.5 V
800
ns
2.0 V
≤ VDD < 2.7 V
1600
ns
2400
ns
SI0 setup time
tSIK2
VDD = 2.0 to 5.5 V
100
ns
(to SCK0
↑)
150
ns
SI0 hold time
tKSI2
400
ns
(from SCK0
↑)
SO0 output delay time
tKSO2
C = 100 pF Note VDD = 2.0 to 5.5 V
300
ns
from SCK0
↓
500
ns
SCK0 rise, fall time
tR2
When external device
160
ns
tF2
expansion function is used
When external
When 16-bit timer
700
ns
device expansion output function is
function is not
used
When 16-bit timer
1000
ns
output function is
not used
(3) Serial Interface (TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
(a) Serial Interface Channel 0
(i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY1
4.5 V
≤ VDD ≤ 5.5 V
800
ns
2.7 V
≤ VDD < 4.5 V
1600
ns
2.0 V
≤ VDD < 2.7 V
3200
ns
4800
ns
SCK0 high/low-level
tKH1
VDD = 4.5 to 5.5 V
tKCY1/2–50
ns
width
tKL1
tKCY1/2–100
ns
SI0 setup time
tSIK1
4.5 V
≤ VDD ≤ 5.5 V
100
ns
(to SCK0
↑)
2.7 V
≤ VDD < 4.5 V
150
ns
2.0 V
≤ VDD < 2.7 V
300
ns
400
ns
SI0 hold time
tKSI1
400
ns
(from SCK0
↑)
SO0 output delay time
tKSO1
C = 100 pF Note
300
ns
from SCK0
↓
Note C is the load capacitance of SCK0 and SO0 output line.
Note C is the load capacitance of SO0 output line.
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