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參數(shù)資料
| 型號(hào)： | UPD78011HGK-XXX-8A8 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 12 X 12 MM, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 30/70頁(yè) |
| 文件大?。?/td> | 540K |
| 代理商： | UPD78011HGK-XXX-8A8 |
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34
PD78011H, 78012H, 78013H, 78014H
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
f = 1 MHz Unmeasured pins returned to 0 V
15
pF
I/O capacitance
P01 to P03, P10 to P17,
f = 1 MHz Unmeasured
P20 to P27, P30 toP37,
15
pF
CIO
pins returned to 0 V
P40 toP47, P50 to P57,
P64 to P67
P60 to P63
20
pF
Unit
MHz
ms
MHz
ms
MHz
ns
2.7 V
≤ VDD ≤ 5.5 V
1
10
1.8 V
≤ VDD < 2.7 V
1
5
VDD = 4.5 to 5.5 V
10
30
Capacitance ( TA = 25
°C, VDD = VSS = 0 V )
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics ( TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
Resonator
Ceramic
resonator
Crystal
resonator
External
clock
Recommended
Circuit
Parameter
Oscillator
frequency (fX) Note 1
Oscillation
stabilization time Note 2
Oscillator
frequency (fX) Note 1
Oscillation
stabilization time Note 2
X1 input
frequency (fX) Note 1
X1 input
high/low level width
(tXH , tXL)
TYP.
MAX.
Test Conditions
After VDD reaches oscil-
lator voltage range MIN.
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wirinin the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
q Wiring should be as short as possible.
q Wiring should not cross other signal lines.
q Wiring should not be placed close to a varying high current.
q The potential of the oscillator capacitor ground should be the same as VSS.
q Do not ground wiring to a ground pattern in which a high current flows.
q Do not fetch a signal from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock, the
subsystem clock should be switched again to the main system clock after the oscillation stabilization
time is secured by the program.
MIN.
2.7 V
≤ VDD ≤ 5.5 V
1
10
1.8 V
≤ VDD < 2.7 V
1
5
4
1.0
10.0
45
500
X1
X2
C2
C1
R1
IC
X1
X2
C2
C1
IC
X1
X2
PD74HCU04
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