參數(shù)資料
型號(hào)： UPD78011HGK-XXX-8A8
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 38/70頁(yè)
文件大?。?/td> 540K
代理商： UPD78011HGK-XXX-8A8
41
PD78011H, 78012H, 78013H, 78014H
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.5tCY
ns
Address setup time
tADS
0.5tCY–30
ns
Address hold time
tADH
50
ns
Data input time from address
tADD1
(2.5+2n)tCY–50
ns
tADD2
(3+2n)tCY–100
ns
Data input time from RD
↓
tRDD1
(1+2n)tCY–25
ns
tRDD2
(2.5+2n)tCY–100
ns
Read data hold time
tRDH
0ns
RD low-level width
tRDL1
(1.5+2n)tCY–20
ns
tRDL2
(2.5+2n) tCY–20
ns
WAIT
↓ input time from RD↓
tRDWT1
0.5tCY
ns
tRDWT2
1.5tCY
ns
WAIT
↓ input time from WR↓
tWRWT
0.5tCY
ns
WAIT low-level width
tWTL
(0.5+2n)tCY+10
(2+2n)tCY
ns
Write data setup time
tWDS
100
ns
Write data hold time
tWDH
Load resistor
≥ 5 k
20
ns
WR low-level width
tWRL1
(2.5+2n) tCY –20
ns
RD
↓ delay time from ASTB↓
tASTRD
0.5tCY–30
ns
WR
↓ delay time from ASTB↓
tASTWR
1.5tCY–30
ns
ASTB
↑ delay time from
tRDAST
tCY–10
tCY+40
ns
RD
↑ in external fetch
Address hold time from
tRDADH
tCY
tCY+50
ns
RD
↑ in external fetch
Write data output time from RD
↑
tRDWD
VDD = 4.5 to 5.5 V
0.5tCY+5
0.5tCY+30
ns
0.5tCY+15
0.5tCY+90
ns
Write data output time from WR
↓
tWRWD
VDD = 4.5 to 5.5 V
5
30
ns
15
90
ns
Address hold time from WR
↑
tWRADH
VDD = 4.5 to 5.5 V
tCY
tCY+60
ns
tCY
tCY+100
ns
RD
↑ delay time from WAIT↑
tWTRD
0.5tCY
2.5tCY+80
ns
WR
↑ delay time from WAIT↑
tWTWR
0.5tCY
2.5tCY+80
ns
(2) Read/Write Operation (TA = –40 to +85
°C, VDD = 2.7 to 5.5 V)
Remarks 1. tCY = TCY/4
2. n indicates number of waits.
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