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參數(shù)資料
| 型號： | UPD7554AGA |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 34/64頁 |
| 文件大?。?/td> | 991K |
| 代理商： | UPD7554AGA |
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3
μ
P
Mne-
monic
Ope-
rands
Operation Code
Operation
Skip
B1
B2
Condition
Transfers the contents of the accumulator
to the four high-order bits of the shift
register and the contents of the memory
addressed by HL to the four low-order bits.
SIO
7–4
←
A
SIO
3–0
←
(HL)
TAMSIO
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
0
Transfers the four high-order bits of the
shift register to the accumulator and the
four low-order bits to the memory
addressed by HL.
TSIOAM
0
0
1
1
1
1
1
1
0
0
1
1
1
0
1
0
A
←
SIO
7–4
(HL)
←
SIO
3–0
SIO
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
Start SIO
Starts shifting.
TIMER
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
Start Timer
Starts timer operation.
Transfers the four high-order bits of
the count register to the accumulator
and the four low-order bits to the
memory addressed by HL.
A
←
CT
7–4
(HL)
←
CT
3–0
TCNTAM
0
0
1
1
1
1
1
1
0
0
1
1
1
0
1
1
IPL
0
1
1
1
0
0
0
0
A
←
Port (L)
Loads the contents of the port specified
by the L register to the accumulator.
Outputs the contents of the accumu-
lator to the port specified by the L
OPL
0
1
1
1
0
0
1
0
Port/Mode reg. (L)
←
A
register or the mode register.
RPBL
Note2
0
1
0
1
1
1
0
0
Port bit (L)
←
0
Resets the bits of ports 8, 10, and 11,
that are specified by the L register.
SPBL
Note2
0
1
0
1
1
1
0
1
Port bit (L)
←
1
Sets the bits of ports 8, 10, and 11,
that are specified by the L register.
HALT
0
0
1
1
1
1
1
1
0
0
1
1
0
1
1
0
Set Halt Mode
Sets the HALT mode.
STOP
0
0
1
1
1
1
1
1
0
0
1
1
0
1
1
1
Set Stop Mode
Sets the STOP mode.
NOP
0
0
0
0
0
0
0
0
No operation
Performs no operation for one
machine cycle.
Note1
S
T
i
I
C
I
Note1.
Instruction Group
2.
SPBL and RPBL are bit-wise set/reset instructions. They perform output to each 4-bit port including the specified bits as well as set and reset operation
(They output the contents of the output latch to bits other than the specified bits.). Before executing these instructions, intialize the contents of the
output latch using the OPL instruction.
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