參數(shù)資料
型號(hào)： UPD7554AGA
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 27/64頁(yè)
文件大?。?/td> 991K
代理商： UPD7554AGA
27
μ
PD7554A, 7554A(A)
3.
STANDBY FUNCTIONS
The
μ
PD7554A provides two types of standby modes (STOP and HALT modes) to save power while the program
is on standby. The STOP and HALT modes are set by the STOP and HALT instructions, respectively. The standby
mode halts program execution, however, it holds the contents of all the internal registers and data memory that
have been stored.
The timer can operate even in the standby mode.
The standby mode is canceled when the test request flag (INTT RQF or INT0/S RQF) is set or by RESET input.
Note that if even one test request flag is set, the device cannot enter either the STOP or HALT mode even though
the STOP or HALT instruction is executed. Before setting the standby mode at a point where a test request flag may
be set, execute the SKI instruction to reset the test request flag.
Table 3-1 relates the STOP mode to the HALT mode. An essential difference between them is found when RC
oscillation supplies the system clock: by stopping the oscillation, the CL output stops in the STOP mode and does
not stop in the HALT mode. Thus the amount of the power consumption of the RC oscillator equals to the difference
in the amounts of the basic power consumption between the STOP mode and HALT mode.
Note that the STOP mode enables the low supply voltage data to be retained in the data memory.
Table 3-1 The Relation Between STOP and HALT Modes
3.1
STOP MODE
The STOP mode stops the RC oscillation and 1/2 divider in the system clock generator. Therefore, the operations
of requiring the system clock stubsystem (CL and
φ
) such as the CPU are stopped. Since the STOP mode allows
operation of the clock control circuit, the timer can operate if the P00 input is selected as the count pulse (CP).
Note that the STOP mode stops only the
φ
signal, allowing the CL output when system clock generation is not
drived by the RC oscillation, but drived by the external CL1 input. In such a case, the STOP mode causes the same
state as in the case of the HALT mode described below. Therefore, the STOP instruction is effective for setting the
STOP mode only during RC oscillation.
3.2
HALT MODE
The HALT mode stops only the 1/2 divider in the system clock generator (allowing operation of the system clock
CL and stopping the CPU clock
φ
). Therefore, the operations of the CPU requiring the
φ
signal is stopped in the HALT
mode. Since the HALT mode allows operation of the clock control circuit, the circuit inputs the CL signal from the
clock generator and the external count clock (P00) to supply the count pulses (CP) for both subsystems selectively
to the timer. Thus, the timer can operate depending on the both-system count pulses and continue counting time.
Setting
Instruction
RC Oscillation
(CL)
φ
P00
CPU
Timer
Cancellation Factor
STOP mode
STOP
×
L
L
INTT RQF
INT0/S RQF
RESET input
×
G
G
×
HALT mode
HALT
G
G
G
G
G
G
: Operation enabled
L
L
: Operation enabled depending on mode selection
×
: Stop
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