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| 型號(hào)： | UPD7554AGA |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 22/64頁 |
| 文件大?。?/td> | 991K |
| 代理商： | UPD7554AGA |
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22
μ
PD7554A, 7554A(A)
2.11 TIMER/EVENT COUNTER
The timer/event counter is based on an 8-bit count register as shown in Fig. 2-12.
Fig. 2-12 Timer/Event Counter
8-BIT COUNT REG
TIMER
Note
RESET
CLR
CP
8
TCNTAM
Note
INTT
(To Test Control Circuit)
Note
Instruction execution
Internal Bus
Count
Holding
Circuit
The 8-bit count register is a binary 8-bit up-counter which is incremented whenever a count pulse (CP) is input.
The register is cleared to 00H when the TIMER instruction is executed, RESET signal is input, or an overflow occurs
(FFH to 00H).
As the count pulse, the clock mode register can select one of the following four. See
2.10 “CLOCK CONTROL
CIRCUIT”
.
1
1
1
CP : CL
×
––, CL
×
–––, CL
×
––––, P00
4
32
256
The count register continues to be incremented as long as count pulses are input. The TIMER instruction clears
the count register to 00H and triggers the timer operation.
The count register is incremented in synchronization with the CP (or the rise of the P00 input when an external
clock is used). On the count reaches 256, the register returns the count value to 00H from FFH, generates the overflow
signal INTT, and sets the INTT test flag INTT RQF.
In this way, the count register counts over from 00H.
To recognize the overflow, test the flag INTT RQF using the SKI instruction.
When the timer/event counter serves as a timer, the reference tiome is determined by the CP frequency. The
precision is determined by the RC oscillation or CL1 external input frequency when the system clock system is
selected and by the P00 input frequency when the P00 input is selected.
The content of the count register can be read at any time by the TCNTAM instruction. This function allows
checking the current time of the timer and counting event pulses input to the P00 input. This enables the number
of even pulses that have been generated so far (event counter function).
The count holding circuit ignores the change of the count pulse (CP) during execution of the TCNTAM instruction.
This is to prevent reading undefined data in the count register using the TCNTAM instruction while the counter is
being updated.
Since the timer/event counter operates the system clock system (CL) or the P00 input for count pulses, it is used
to cancel the HALT mode which stops the CPU clock
φ
as well as the STOP mode which stops the system clock CL.
(See
3 “STANDBY FUNCTIONS”
.)
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