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參數(shù)資料
| 型號： | UPD7554AGA |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 20/64頁 |
| 文件大?。?/td> | 991K |
| 代理商： | UPD7554AGA |
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20
μ
PD7554A, 7554A(A)
2.9
SYSTEM CLOCK GENERATOR
The system clock generator contains an RC oscillator, 1/2 divider, and standby (STOP/HALT) mode control circuit.
Fig. 2-9 System Clock Generator
STANDBY RELEASE
RESET ( )
(To CPU)
φ
CL (System Clock)
RESET (High)
HALT
Note
STOP
Note
HALT F/F
Q
S
R
Q
S
R
STOP F/F
CL2
CL1
C
R
1/2
RC
Oscillator
Note
Instruction execution
Oscillator
Stop
The RC oscillator oscillates with an external resistor R connected to pins CL1 and CL2. (A capacitor C is
incorporated.)
The RC oscillator serves merely as a reverse buffer if inputs an external clock through the CL1 input.
The RC oscillator outputs the system clock (CL) which is 1/2 divided to the CPU clock (
φ
).
The control circuit in the standby mode consists mainly of STOP F/F and HALT F/F.
The STOP F/F is set by the STOP instruction, blocking any clock from being supplied. The STOP F/F stops RC
oscillation during operation of the RC oscillator (STOP mode).
The STOP F/F is reset by the STANDBY RELEASE signal (which goes active when even one test request flag is
input) or at the fall of the RESET input, to cause the RC oscillator to start oscillation and supplying each clock.
The HALT F/F is set by the HALT instruction to disable the input to the 1/2 divider which generates the CPU clock
φ
, stopping only the CPU clock
φ
(HALT mode).
The HALT F/F is set and reset as in the case of the STOP F/F. Resetting the HALT F/F cause the RC oscillator to
start supplying the CPU clock
φ
.
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