
28
μ
PD75238
Fig. 3-2 Program Memory Map
Caution The start address of an interrupt vector shown above consists of 14 bits. So, the start address
must be set within a 16K-byte space (0000H to 3FFFH).
Remark
In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address
with only the low-order 8 bits of the PC changed.
Internal reset start address
BRCB !caddr
instruction
branch address
MBE RBE
Internal reset start address
INTBT/INT4 start address
MBE RBE
INTBT/INT4 start address
MBE RBE
INT0 start address
INT0 start address
MBE RBE
INT1 start address
INT1 start address
MBE RBE
INTSO start address
INTSO start address
MBE RBE
INTT0 start address
INTT0 start address
MBE RBE
INTTPG start address
INTTPG start address
MBE RBE
INTKS start address
INTKS start address
GETI instruction reference table
0000H
0002H
0004H
0006H
0008H
000AH
000CH
000EH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
4000H
4FFFH
5000H
5FFFH
6000H
6FFFH
7000H
7F7FH
CALL !addr
instruction
branch address
Branch/call
address specified
in GETI instruction
CALLF !faddr
instruction
entry address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRA !addr
instruction
branch address
CALLA !addr
instruction
branch address
BR $addr1 instruction
relative branch
address (–15 to –1,
+2 to +16)
BR !addr
instruction
branch address
(low-order 8 bits)
(high-order 6 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)