- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379502 > UPD75238 (NEC Corp.) 4 BIT SINGLE-CHIP MICROCOMPUTER PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD75238 |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 134/190頁(yè) |
| 文件大?。?/td> | 1702K |
| 代理商： | UPD75238 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)當(dāng)前第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)
134
μ
PD75238
Table 5-2 Set Signals of Interrupt Request Flags
(2) Noise eliminator and edge detection mode register
As shown in Fig. 5-2 and Fig. 5-3, the INT0, INT1, and INT2 pins are configured as external interrupt input
pins that enable detection edge selection.
In addition, INT0 is provided with a noise elimination function based on a sampling clock. Basically, the
noise eliminator eliminates pulses narrower than two sampling clock cycles
Note
as noise. However, it may
accept pulses wider than one sampling clock cycle as interrupt signals depending on the sampling timing.
It surely accepts pulses wider than two sampling clock cycles as interrupt signals.
INT0 has two sampling clocks
Φ
and f
X
/64, either of which can be selected according to bit 3 (IM03) of the
edge detection mode register (see
Fig. 5-4
).
The IRQ2 is set by detecting a rising edge of the INT2 pin input.
The edge detection mode registers (IM0 and IM1) used to select a detection edge have the format shown
in Fig. 5-4. A 4-bit memory manipulation instruction is used to set IM0 or IM1. A RESET input clears all
bits to 0, and a rising edge is selected for INT0, INT1, and INT2.
Note
When a sampling clock is
Φ
, two sampling clock cycles are 2t
CY
.
When a sampling clock is f
X
/64, two sampling clock cycles are 128/f
X
.
Cautions 1. Since the INT0 pin input is sampled with a clock, INT0 does not operate in a standby mode.
2. When INT0/P10 is used as a port, pulses input from INT0/P10 go through the noise
eliminator. So the input pulses must be wider than two sampling clock cycles.
Set by a reference time interval signal from the basic interval timer.
Set by a detected rising or falling edge of an INT4/P00 pin input signal.
Set by a detected edge of an INT0/P10 pin input signal. The detection edge is specified
by the INT0 mode register (IM0).
Set by a detected edge of an INT1/P11 pin input signal. The detection edge is specified
by the INT1 mode register (IM1).
Set by a serial data transfer completion signal for the serial interface.
Set by a match signal from timer/event counter 0.
Set by a match signal from the timer/pulse generator.
Set by a key scan timing signal from the display controller.
Set by a signal from the clock timer.
Set by a detected rising edge of an INT2/P12 pin input signal.
IRQBT
IRQ4
IRQ0
IRQ1
IRQCSI0
IRQT0
IRQTPG
IRQKS
IRQW
IRQ2
Set signal of interrupt request flag
Interrupt
Interrupt
request flag
#
IEBT
IE4
IE0
IE1
IECSI0
IET0
IETPG
IEKS
IEW
IE2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD75238GJ | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| UPD7527A | 4-Bit, Single-Chip CMOS Microcomputers With FIP Driver |
| UPD7528A | 4-Bit, Single-Chip CMOS Microcomputers With FIP Driver |
| UPD7527AC | 4-Bit, Single-Chip CMOS Microcomputers With FIP Driver |
| UPD7527ACU | 4-Bit, Single-Chip CMOS Microcomputers With FIP Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD753012AGC-P33-8BT-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD753016AGC-P29-8BT | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD75304GF-407-3B9 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD75306G182 | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD75308F478 | 制造商:Panasonic Industrial Company 功能描述:IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。