
148
μ
PD75238
Table 7-1 Statuses of the Hardware after a Reset (1/2)
Hardware
Carry flag (CY)
Skip flags (SK0 to SK2)
Interrupt status flags (IST1, IST2)
Bank enable flags (MBE, RBE)
Counter (BT)
Mode register (BTM)
Counter (T0)
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT F/F
Mode register (WM)
Modulo registers (MODH, MODL)
Mode register (TPGM)
Counter (T1)
Mode register (TM1)
Gate control register (GATEC)
Shift register (SIO0)
Operation mode register
(CSIM0)
SBI control register (SBIC)
Slave address register (SVA)
P01/SCK0 output latch
Shift register (SIO1)
Operation mode register
(CSIM1)
Serial transfer end flag (EOT)
RESET input during operation
RESET input in a standby mode
Program counter (PC)
PSW
Data memory (RAM)
General registers (X, A, H, L, D, E, B, C)
Bank select register (MBS, RBS)
Stack pointer (SP)
Stack bank select register (SBS)
Basic interval
timer
Timer/event
counter
Watch timer
Timer/pulse
generator
Event counter
Serial interface
(Channel 0)
Serial interface
(Channel 1)
Low-order 6 bits at address 0000H
in program memory are set in PC
bits 13 to 8, and the data at address
0001H are set in PC bits 7 to 0.
Held
0
0
Bit 6 at address 0000H in pro-
gram memory is set in RBE, and
bit 7 is set in MBE.
Held
Held
0, 0
Undefined
Undefined
Undefined
0
0
FFH
0
0, 0
0
Held
0
0
0
0
Held
0
0
Held
1
Held
0
0
Low-order 6 bits at address 0000H
in program memory are set in PC
bits 13 to 8, and the data at address
0001H are set in PC bits 7 to 0.
Undefined
0
0
Bit 6 at address 0000H in pro-
gram memory is set in RBE, and
bit 7 is set in MBE.
Undefined
Undefined
0, 0
Undefined
Undefined
Undefined
0
0
FFH
0
0, 0
0
Held
0
0
0
0
Undefined
0
0
Undefined
1
Undefined
0
0