
54
μ
PD75237
(4)
System clock control register (SCC)
The SCC is a 4-bit register to select the CPU clock
Φ
with the least significant bit and to control main system
clock oscillation stop with the most significant bit (refer to
Fig. 4-16
).
Although SCC.0 and SCC.3 are located at the same data memory address, both bits cannot be changed
simultaneously. Thus, SCC.0 and SCC.3 are set by the bit manipulation instruction. SCC.0 and SCC.3 can always
be bit manipulated irrespective of the MBE contents.
Main system clock oscillation can be stopped by setting SCC.3 only when in operation with the subsystem
clock. Oscillation when in operation with the main system clock is stopped by the STOP instruction.
RESET input clears SCC to “0”.
Fig. 4-16 System Clock Control Register Format
FB7H
SCC3
SCC0
SCC
3
2
1
0
Address
Symbol
0
0
1
1
Main system clock
Subsystem clock
Subsystem clock
Oscillation enabled
Oscillation stop
System Clock
Selection
Main System Clock
Oscillation
Setting prohibited
SCC3
SCC0
0
1
0
1
Note
1. A maximum of 1/f
XT
is required to change the system clock. Thus, when stopping the main system clock
oscillation, change the clock to the subsystem clock and set SCC.3 following the passage of more than
the machine cycles described in Table 4-2.
2. The normal STOP mode cannot be set if oscillation is stopped by setting SCC.3 while in operation with
the main system clock.
3. If SCC.3 is set to “1”, X1 input is internally short-circuited to V
SS
(GND potential) to suppress crystal
oscillator leakage. Thus, when using an external clock for the main system clock do not set SCC.3 to
“1”.
4. When PCC = 0001B (
Φ
= f
X
/16 selected), do not set SCC.0 to “1”. When switching from the main system
clock to the subsystem clock, do so after setting PCC to another value (PCC
≠
0001B).
Do not set PCC = 0001B while in operation with the subsystem clock.