參數(shù)資料
型號(hào)： UPD75048GC
廠(chǎng)商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 37/68頁(yè)
文件大?。?/td> 538K
代理商： UPD75048GC
37
μ
PD75048
Timer/Event
Counter
Counter (T0)
Modulo Register
(TMOD0)
0
0
FFH
FFH
Mode Register (TM0)
TOE0, TOUT F/F
0
0
0, 0
0, 0
Watch Timer
Mode Register (WM)
0
0
9. RESET FUNCTION
When the RESET signal is input, the
μ
PD75048 is reset and each hardware is initialized as indicated
in Table 9-1. Fig. 9-1 shows the reset operation timing.
RESET input
Wait
(31.3ms/4.19MHz)
Operation mode
or standby mode
HALT mode
Operation mode
Internal reset operation
Fig. 9-1 Reset Operation by RESET Input
Table 9-1 Status of Each Hardware after Reset (1/2)
Hardware
RESET Input in Standby Mode
RESET Input During Operation
Program Counter (PC)
The contents of the lower 5 bits
of address 0000H of the program
memory are set to PC12-8, and
the contents of address 0001H
are set to PC7-0.
The contents of the lower 5 bits
of address 0000H of the program
memory are set to PC12-8, and
the contents of address 0001H
are set to PC7-0.
PSW
Carry Flag (CY)
Retained
Undefined
Skip Flag (SK0-2)
Interrupt Status Flag (IST0)
Bank Enable Flag (MBE)
The contents of bit 7 of address
0000H of the program memory is
set to MBE.
Stack Pointer (SP)
Undefined
Undefined
Data Memory (RAM)
Retained *
Undefined
Data Memory
(EEPROM)
EEPROM
Contents of address being
written is undefined.
Contents of address being
written is undefined.
EEPROM Write Control
Register
General-Purpose Register
(X, A, H, L, D, E, B, C)
Retained
Undefined
Bank Selection Register (MBS)
Basic Interval
Timer
Counter (BT)
Mode Register (BTM)
Undefined
Undefined
The contents of bit 7 of address
0000H of the program memory is
set to MBE.
*: The data at the addresses 0F8H-0FDH of data memory is undefined by RESET input.
0
0
0
0
0
0
0
0
0
0
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