參數(shù)資料
型號: UPD75048GC
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 4位單片機
文件頁數(shù): 26/68頁
文件大?。?/td> 538K
代理商: UPD75048GC
26
μ
PD75048
6.5
WATCH TIMER
The
μ
PD75048 has a built-in 1-ch watch timer. The clock timer has the following functions.
Sets the test flag (IRQW) with 0.5sec interval.
The standby mode can be released by IRQW.
0.5 second interval can be generated either from the main system clock or subsystem clock.
Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is
convenient for program debugging, test, etc.
Arbitrary frequency (2.048kHz/4.096kHz/32.768kHz) can be output to the P23/BUZ pin. This can be
used for beep and system clock frequency trimming.
The frequency divider circuit can be cleared so that zero second clock start is possible.
( ) is for f
X
= 4.194304 MHz, f
XT
= 32.768 KHz.
Fig. 6-4 Clock Timer Block Diagram
f
W
(32.768 kHz)
Frequency divider
Selector
Selector
Clear
Selector
Output buffer
P23/BUZ
Bit 2 of PMGB
Port 2
input/output
mode
P23
output
latch
PORT2.3
WM
WM7
0
WM5
WM4
WM3
WM2
WM1
WM0
Bit test
instruction
Internal bus
8
4 kHz 2 kHz
INTW
(
)
2 Hz
0.5 sec
( )
f
W
2
7
(256 Hz:3.91 ms)
f
X
128
(32.768 kHz)
f
XT
(32.768 kHz)
From the
clock
generator
f
w
2
14
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