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參數(shù)資料
| 型號： | UPD75048GC |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 34/68頁 |
| 文件大?。?/td> | 538K |
| 代理商： | UPD75048GC |
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34
μ
PD75048
6.10
BIT SEQUENTIAL BUFFER .... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,
addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore,
this buffer is very useful for processing long data in bit units.
Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register.
Fig. 6-9 Bit Sequential Buffer Format
Address
Bit
Symbol
L register
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
L = F
L = C L = B
L = 8
L = 7
L = 4
L = 3
L = 0
BSB3
BSB2
BSB1
BSB0
DECS L
INCS L
FC3H
FC2H
FC1H
FC0H
7. INTERRUPT FUNCTIONS
The
μ
control is also possible.
The
μ
PD75048 is also provided with two types of test sources, of which INT2 was two types of edge
detection testable inputs.
The interrupt control circuit of the
μ
PD75048 has these functions:
Hardware controlled vector interrupt function which can control whether or not to accept an
interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME).
The interrupt start address can be arbitrarily set.
Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of
software).
Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
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