
APPENDIX  B   REVISION  HISTORY
User’s Manual  U15862EJ3V0UD
756
(2/3)
Edition
Major Revision from Previous Edition
Applied to:
Addition of setting procedures in 
7.4.2  PPG output operation
Addition of 
Figure 7-6  Configuration of PPG Output
Addition of 
Figure 7-7  PPG Output Operation Timing
Addition of setting procedures in 
7.4.3  Pulse width measurement
Addition of setting procedures and addition of 
Caution 2 
in 
7.4.4  Operation as external
event counter
Addition of setting procedures and addition of 
Caution 
in 
7.4.5  Square-wave output
operation
Addition of setting procedures in 
7.4.6  One-shot pulse output operation
Addition of 
Caution 2 
in 
7.4.6 (1) One-shot pulse output with software trigger (16-bit
timer/event counters 00, 01, 04 and 05 only)
Addition of 
Caution 2 
in 
7.4.6 (2) One-shot pulse output with external trigger (16-bit
timer/event counters 04 and 05 only)
Addition of 
Caution 
in 
7.4.7 (10) (b) When setting CR0n0, CR0n1 to compare mode
CHAPTER 7  16-BIT
TIMER/EVENT
COUNTERS 00 TO 05
Addition of description in 
CHAPTER 8  8-BIT TIMER/EVENT COUNTERS 50 AND 51
CHAPTER 8  8-BIT
TIMER/EVENT
COUNTERS 50 AND 51
Addition of description in 
CHAPTER 9  8-BIT TIMERS H0 AND H1
Addition of 
Caution 3 
in 
9.3 (1) (a) 8-bit timer H mode register 0 (TMHMD0)
Addition of 
Caution 3 
in 
9.3 (1) (b) 8-bit timer H mode register 1 (TMHMD1)
Addition of 
Caution 2 
in 
Figure 9-7  Transfer Timing
Addition of 
Caution 4 
in 
9.4.3 (4) Timing chart
CHAPTER 9  8-BIT
TIMERS H0 AND H1
Addition of 
13.4  Relationship Between Analog Input Voltage and A/D Conversion
Result
Addition of 
13.6 (3) A/D converter sampling time and A/D conversion start delay
time
Addition of 
13.7  How to Read A/D Converter Characteristics Table
CHAPTER 13  A/D
CONVERTER
Addition of description in 
CHAPTER 15  ASYNCHRONOUS SERIAL INTERFACE
(UART)
Modification of description in 
Figure 15-6  Continuous Transmission Starting
Procedure
CHAPTER 15
ASYNCHRONOUS
SERIAL INTERFACE
(UART)
Addition of description in 
CHAPTER 16  CLOCKED SERIAL INTERFACE 0 (CSI0)
CHAPTER 16  CLOCKED
SERIAL INTERFACE 0
(CSI0)
Modification of description in 
CHAPTER 17  CLOCKED SERIAL INTERFACE A (CSIA)
WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
CHAPTER 17  CLOCKED
SERIAL INTERFACE A
(CSIA) WITH AUTOMATIC
TRANSMIT/RECEIVE
FUNCTION
Addition of description in 
CHAPTER 18  I
2
C BUS
CHAPTER 18  I
2
C BUS
Addition to 
Cautions 
in 
Table 25-1  Wiring Between 
μ
PD70F3210 and 70F3210Y
(V850ES/KF1), and PG-FP3
Addition of 
Figure 25-1  Wiring Example of V850ES/KF1 Flash Writing Adapter (FA-
80GC-8BT, FA-80GK-9EU)
3rd
Addition of 
Cautions 
in 
Table 25-2  Wiring Between 
μ
PD70F3214 and 70F3214Y
(V850ES/KG1), and PG-FP3
CHAPTER 25  FLASH
MEMORY