
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User
’
s Manual U15862EJ3V0UD
367
8.4.7 Square-wave output operation (16-bit resolution)
The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with a 16-bit register that can be used only during
cascade connection.
The 16-bit resolution timer/event counter mode is selected by setting the TMC514 bit of 8-bit timer mode control
register 51 (TMC51) to 1.
8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer
compare register 5 (CR5).
Setting method
<1>
Set each register.
TCL50 register:
TCL50 selects the count clock (t)
(The TCL51 register does not have to be set in cascade connection)
Compare value (N) ... Lower 8 bits (settable from 00H to FFH)
Compare value (N) ... Higher 8 bits (settable from 00H to FFH)
TMC50, TCM51 registers: Stops count operation, selects the mode in which clear & start occurs on a
match between the TM5 register and CR5 register.
CR50 register:
CR51 register:
LVS50
LVR50
Timer Output F/F Status Settings
1
0
High-level output
0
1
Low-level output
Enables timer output F/F inversion, and enables timer output.
TMC50 register = 00001011B or 00000111B
TMC51 register = 00010000B
<2>
Set the TCE51 bit of the TMC51 register to 1. Then set the TCE50 bit of the TMC50 register to 1 to start
the count operation.
When the values of the TM5 register and the CR5 register connected in cascade match, the TO50 timer
output F/F is inverted. Moreover, INTTM50 is generated and the TM5 register is cleared to 0000H.
Then, the timer F/F is inverted during the same interval and a square wave is output from the TO50 pin.
<3>
<4>
Frequency = 1/2t(N + 1): N = 0000H to FFFFH