
CHAPTER 6 CLOCK GENERATION FUNCTION
User
’
s Manual U15862EJ3V0UD
297
(b) Example of setting subclock operation
<1>
MCK
←
0:
<2>
Insert wait cycles by program and wait until the oscillation of the main clock has been stabilized.
<3>
CK3
←
0:
Use of a bit manipulation instruction is recommended. Do not change
CK2, CK1, and CK0 bits.
<4>
Main clock operation:
It takes up to the following number of instructions after the CK3 bit is
set until the main clock operation specified by CK2 to CK0 is started.
Max.: (1/subclock frequency)
Therefore, read the CLS bit to check if the subclock operation has
started.
→
main clock operation
Main clock oscillation starts.
(2) Power save control register (PSC)
The power save control register (PSC) is a special register. Data can be written to this register only in a
combination of specific sequences (refer to
3.4.7 Special registers
).
This register can be read or written in 8-bit or 1-bit units.
NMI2M
PSC
0
NMI0M
INTM
0
0
STP
0
INTWDT2 request enabled
INTWDT2 request disabled
NMI2M
0
1
Controls non-maskable interrupt request (INTWDT2) from watchdog timer 2
Note 1
NMI request enabled
NMI request disabled
NMI0M
0
1
Controls non-maskable interrupt request (NMI) from NMI pin
Note 1
INTxx request enabled
INTxx request disabled
INTM
0
1
Controls all maskable interrupt requests (INTxx)
Note 1
Normal mode
Standby mode
Note 2
STP
0
1
Sets operation mode
After reset: 00H R/W After reset: FFFFF1FEH
< >
< >
< >
< >
Notes 1.
Setting these bits is valid only in the STOP mode.
2.
Set STOP or IDLE mode using the PSM bit of the PSMR register.
Remark
For details of INTxx, refer to
Tables 19-1
to
19-3 Interrupt Source Lists
.