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參數(shù)資料
| 型號： | UM_S3C49F9X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3C49F9X User’s Manual |
| 中文描述： | S3C49F9X用戶手冊 |
| 文件頁數(shù)： | 48/74頁 |
| 文件大?。?/td> | 653K |
| 代理商： | UM_S3C49F9X |
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S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION
47
4.10.9 Status & Alternate Status Register (Address -1F7[177]&3F6[376]; Offset 7, Eh):
These registers return the PC Card status when read by the host. Reading the Status register does clear a
pending interrupt while reading the Auxiliary Status register does not. The meaning of the status bits is
described as follows:
D7
D6
D5
D4
BUSY
RDY
DWF
DSC
Bit 7 (BUSY)
The busy bit is set when the PC Card has access to the command buffer and registers
and the host is locked out from accessing the command register and buffer. No other bits in this register
are valid when this bit is set to a 1.
Bit 6 (RDY)
RDY indicates whether the device is capable of performing PC Card operations. This bit
is cleared at power up and remains cleared until the PC Card is ready to accept a command.
Bit 5 (DWF)
This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC)
This bit is set when the PC Card is ready. This bit is cleared at power up.
Bit 3 (DRQ)
The
Data Request is set when the PC Card required and that information be transferred
either to or from the host through the Data register.
Bit 2 (CORR)
This
bit is set when a Correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector read operation.
Bit 1
This bit is always set to 0.
Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits
in the Error register contain additional information describing the error.
D3
DRQ
D2
D1
0
D0
ERR
CORR
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