參數(shù)資料
型號(hào): UM_S3C49F9X
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: S3C49F9X User’s Manual
中文描述: S3C49F9X用戶手冊(cè)
文件頁(yè)數(shù): 44/74頁(yè)
文件大小: 653K
代理商: UM_S3C49F9X
S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION
43
4.10 ATA Registers
The following section describes the hardware registers used by the host software to issue commands to
the CompactFlash device. These registers are often collectively referred to as the "task file."
Note:
In accordance with the PCMCIA specification: each of the registers below which is located at an odd offset
address may be accessed at its normal address and also the corresponding even address (normal address –1) using
data bus lines (D15-D8) when –CE1 is high and –CE2 is low unless –IOIS16is high (not asserted) and an I/O cycle is
being performed.
4.10.1 Data Register (Address -1F0[170]; Offset 0,8,9):
The Data Register is a 16bit register, and it used to transfer data blocks between the PC Card data buffer
and the Host. This register overlaps the Error Register.
The table below describes the combinations of data register access and is provided to assist in
understanding the overlapped Data Register and Error/Feature Register rather than to attempt to define
general PCMCIA word and byte access modes and operations. See the PCMCIA PC Card Standard
Release 3.0 for definitions of the Card Accessing Modes for I/O and Memory cycles.
Note:
Because of the overlapped register, access to the 1f1h, 171h or offset 1 are not defined for word (-CE2 = 0 and –
CE1 = 0) operations. These accesses are treated as accesses to the Word Data Register.
The duplicated registers at offsets 8,9 and Dh have no restrictions on the operations that can be performed
by the socket.
Data Register
-CE2
-CE1
Word Data Register
0
0
Even Data Register
1
0
Odd Data Register
1
0
Odd Data Register
0
1
Error / Feature Register
1
0
Error / Feature Register
0
1
Error / Feature Register
0
0
A0
×
0
1
×
1
×
×
Offset
0,8,9
0,8
9
8,9
1,Dh
1
Dh
Data Bus
D15-D0
D7-D0
D7-D0
D15-D8
D7-D0
D15-D8
D15-D8
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