參數(shù)資料
型號(hào): UM_S3C49F9X
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: S3C49F9X User’s Manual
中文描述: S3C49F9X用戶手冊(cè)
文件頁(yè)數(shù): 33/74頁(yè)
文件大?。?/td> 653K
代理商: UM_S3C49F9X
S3C49F9X SOLID DISK CONTROLLER CARD CONFIGURATION
32
4.3 Card Configuration and Status Register (Address 202h in attribute memory)
The Card Configuration and Status Register contains information about the Card's condition.
Operation
D7
D6
D5
D4
D3
D2
D1
D0
Read
Changed
SigChg
IOis8
0
0
PwrDwn
Int
0
Write
0
SigChg
IOis8
0
0
PwrDwn
0
0
Changed
set to one (1). When the Changed bit is set, -STSCHG Pin 46 is held low if the SigChg bit is a One (1)
and the PC Card is configured for the I/O interface.
SigChg
This bit is set and reset by the host to enable and disable a state-change signal from
the Status Register, the Changed bit control pin 46 the Changed Status signal. If no state change signal is
desired, this bit should be set to zero (0) and pin 46 (-STSCHG) signal will be held high while the PC Card
is configured for I/O.
IOis8
The host sets this bit to a one (1) if the PC Card is to be configured in an 8 bit I/O
Mode. The PC Card is always configured for both 8- and 16-bit I/O, so this bit is ignored.
PwrDwn
This bit indicates whether the host requests the PC Card to be in the power saving or
active mode. When the bit is one (1), the PC Card enters a power down mode. When zero (0), the host is
requesting the PC Card to enter the active mode. The PCMCIA Rdy/-Bsy value becomes BUSY when this
bit is changed. Rdy/-Bsy will not become Ready until the power state requested has been entered. The
PC Card automatically powers down when it is idle and powers back up when it receives a command.
Int
This bit represents the internal state of the interrupt request. This value is available
whether or not I/O interface has been configured. This signal remains true until the condition which
caused the interrupt request has been serviced. If interrupts are disabled by the -IEN bit in the Device
Control Register, this bit is a zero (0).
Indicates that one or both of the Pin Replacement register CRdy, or CWProt bits are
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