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| 型號： | UM_S3C49F9X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3C49F9X User’s Manual |
| 中文描述： | S3C49F9X用戶手冊 |
| 文件頁數(shù)： | 11/74頁 |
| 文件大?。?/td> | 653K |
| 代理商： | UM_S3C49F9X |
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S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION
11
Table 2-3 Pin description for host interface(Cont.)
Signal
Name
100-Pin
Number
I/O
Description
XCE1
23
I
CARD ENABLE : These input signals are used both to select the card and to
indicate to the card whether a byte or a word operation is being performed.
-CE2 always accesses the odd byte of the word. -CE1 accesses the even byte or
the Odd byte of the word depending on A0 and -CE2. A multi-plexing scheme
based on A0, -CE1, -CE2 allows 8 bit hosts to access all data on XDB0-XDB7.
See tables 3-7,3-8,4-3 and 4-4.
This signal is the same as the PC card memory mode signal in PC Card I/O
mode.
In the True IDE mode, CS0 is the chip select for the task file registers while CS1
is used to select the alternate status register and the device control register.
XCE2
24
I
XOE
21
I
OUTPUT ENABLE : This is an output enable strobe generated by the host
interface. It is used to read data from the PC Card in memory mode and to read
the CIS and configuration registers.
In PC Card I/O mode, this signal is used to read the CIS and configuration
registers.
To enable True IDE mode this input should be grounded by the host.
XWE
15
I
WRITE ENABLE : This is a signal driven by the host and used for strobing
memory write data to the registers of the PC Card when the card is configured in
the memory interface mode. It is also used for writing the configuration registers.
In PC Card I/O mode, this signal is used for writing the configuration registers.
In True IDE mode, this input signal is not used and should be connected to VCC
by the host.
XWAIT
1
O
WAIT : The -WAIT signal is driven low by the PC Card to signal the host to delay
completion of a memory or I/O cycle that is in progress.
IORDY : In True IDE mode, this output signal may be used as IORDY.
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