參數(shù)資料
型號(hào): TUSB3410VF
英文描述: BUS CONTROLLER
中文描述: 總線控制器
文件頁(yè)數(shù): 51/92頁(yè)
文件大?。?/td> 317K
代理商: TUSB3410VF
7
5
7.1.6
MCR: Modem-Control Register (Addr:FFA4)
This register provides control for modem interface I/O and definition of the flow control mode.
7
6
5
4
3
2
1
0
LCD
LRI
RTS
DTR
SEN
LOOP
RCVE
URST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIT
0
NAME
URST
RESET
0
FUNCTION
Uart soft reset. This bit can be used by the MCU to reset the UART.
URST = 0
Normal operation. Writing a 0 by MCU has no effect.
URST = 1
When the MCU writes a 1 to this bit, a UART reset is generated (ORed with hard reset). When
the UART exits the reset state, URST is cleared. The MCU can monitor this bit to determine if the
UART completed the reset cycle.
1
RCVE
0
Receiver enable bit. This bit is valid only when 485E in FCRL is 1 (RS485 mode). When 485E = 0, this bit has
no effect on the receiver.
RCVE = 0
When 485E = 1, the UART receiver is disabled when RTS = 1, i.e., when data is being transmitted,
the UART receiver is disabled.
RCVE = 1
When 485E = 1, the UART receiver is enabled regardless of the RTS state, i.e., UART receiver
is enabled all the time. This mode can be used to detect collisions on the RS-485 bus when
received data does not match transmitted data.
2
LOOP
0
This bit controls the normal-/loop-back mode of operation (see Figure 7
1).
LOOP = 0
Normal operation
LOOP = 1
Enable loop-back mode of operation. In this mode the following occur:
SOUT is set high
SIN is disconnected from the receiver input.
The transmitter serial output is looped back into the receiver serial input.
The four modem-control inputs: CTS, DSR, DCD, and RI are disconnected.
DTR, RTS, LRI and LCD are internally connected to the four modem-control inputs, and read
in the MSR register as follows:
DTR is reflected in MSR[4] bit
RTS is reflected in MSR[5] bit
LRI is reflected in MSR[6] bit
LCD is reflected in MSR[7] bit
3
RSV
0
Reserved
4
DTR
0
This bit controls the state of the DTR output pin (see Figure 7
1). This bit has no effect when auto-flow control
is used or when 485E = 1 (in FCRL register).
DTR = 0
Forces the DTR output pin to inactive (high)
DTR = 1
Forces the DTR output pin to active (low)
5
RTS
0
This bit controls the state of the RTS output pin (see Figure 7
1). This bit has no effect when auto-flow control
is used or when 485E = 1 (in FCRL register).
RTS = 0
Forces the RTS output pin to inactive (high)
RTS = 1
Forces the RTS output pin to active (low)
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