參數(shù)資料
型號: TUSB3410VF
英文描述: BUS CONTROLLER
中文描述: 總線控制器
文件頁數(shù): 15/92頁
文件大?。?/td> 317K
代理商: TUSB3410VF
2
3
Table 2
1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CLKOUT
22
O
Clock output (controlled by CLKOUTEN and CLKSLCT in MODECNFG register (see Section 5.1.5
and Note 1)
CTS
13
I
UART: Clear to send (see Note 4)
DCD
15
I
UART: Data carrier detect (see Note 4)
DM
7
I/O
Upstream USB port differential data minus
DP
6
I/O
Upstream USB port differential data plus
DSR
14
I
UART: Data set ready (see Note 4)
DTR
21
O
UART: Data terminal ready (see Note 1)
GND
8, 18, 28
GND
Digital ground
P3.0
32
I/O
Port-3.0 (see Notes 3, 4, 5, and 8)
P3.1
31
I/O
Port-3.1 (see Notes 3, 4, 5, and 8)
P3.3
30
I/O
Port-3.3 (see Notes 3, 4, 5, and 8)
P3.4
29
I/O
Port-3.4 (see Notes 3, 4, 5, and 8)
PUR
5
O
Pull-up resistor connection (see Note 2)
RESET
9
I
Controller master reset signal (see Note 4)
RI/CP
16
I
UART: Ring indicator (see Note 4)
RTS
20
O
UART: Request to send (see Note 1)
Master I2C controller: clock signal (see Note 1)
Master I2C controller: data signal (see Notes 1 and 5)
SCL
11
O
SDA
10
I/O
SIN/IR_SIN
17
I
UART: Serial input data / IR Serial data input (see Note 6)
SOUT/IR_SOUT
19
O
UART: Serial output data / IR Serial data output (see Note 7)
SUSPEND
2
O
Suspend condition signal (see Note 3)
TEST0
23
I
Test input (for factory test only) (see Note 5)
TEST1
24
I
Test input (for factory test only) (see Note 5)
VCC
3, 25
PWR
3.3 V
VDD18
4
PWR
1.8-V Supply. An internal voltage regulator generates this supply voltage when terminal VREGEN
is asserted. When VREGEN is deasserted, 1.8 V must be supplied externally.
VREGEN
1
I
This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator in the core.
WAKEUP
12
I
Remote wake-up request pin. When low, wakes up system (see Note 5)
X1/CLKI
27
I
12-MHz crystal input or clock input
X2
NOTES:
26
O
12-MHz crystal output
1. 3-state CMOS output (
±
4-mA drive/sink)
2. 3-state CMOS output (
±
8-mA drive/sink)
3. 3-state CMOS output (
±
12-mA drive/sink)
4. TTL-compatible, hysteresis input
5. TTL-compatible, hysteresis input, with internal 100-
μ
A active pullup
6. TTL-compatible input without hysteresis, with internal 100-
μ
A active pullup
7. Normal or IR mode: 3-state CMOS output (
±
4-mA drive/sink)
8. The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two
clock cycles and then the output is tristated.
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