參數(shù)資料
型號(hào): TUSB3410VF
英文描述: BUS CONTROLLER
中文描述: 總線控制器
文件頁(yè)數(shù): 42/92頁(yè)
文件大?。?/td> 317K
代理商: TUSB3410VF
6
2
6.1.1
DMACDR1: DMA Channel Definition Register (UART Transmit Channel) (Addr:FFE0)
These registers are used to define the EDB number that the DMA uses for data transfer to the UARTS. In addition,
these registers define the data transfer direction and selects X or Y as the transaction buffer.
7
6
5
4
3
2
1
0
EN
R/W
INE
R/W
CNT
R/W
XY
R/W
T/R
R/O
E2
R/W
E1
R/W
E0
R/W
BIT
2
0
3
NAME
E[2:0]
T/R
RESET
0
0
FUNCTION
Endpoint descriptor pointer. This field points to a set of EDB registers that is to be used for a given transfer.
This bit is always zero, indicating that the DMA data transfer is from SRAM to the UART TDR register. (The MCU
cannot change this bit.)
X/Y buffer select bit. Valid only when CNT = 0
XY = 0
XY = 1
Next buffer to transmit/receive is the Y buffer
DMA continuous transfer control bit. This bit defines the mode of the DMA transfer.
CNT = 0
Burst mode:
The DMA stops the transfer when the byte count is zero or when a partial packet has been
received (byte count < 64). At the end of transfer, the high-to-low transition of EN interrupts the MCU (if
enabled). In this mode, the X/Y bit is set by the MCU to define the current buffer (X or Y).
CNT = 1
Continuous mode:
In this mode, the DMA and UBM alternate between the X- and Y-buffers. The DMA
sets the X/Y bit and the UBM uses it for the transfer. The DMA alternates between the X-/Y-buffers and
continues transmitting (from X-/Y-buffer) without MCU intervention. The DMA terminates, and interrupts
the MCU, under the following conditions:
1. When the UBM byte count < buffer size (in EDB), the DMA transfers the partial packet and interrupt
the MCU on completion.
2. Transaction timer expires. The DMA interrupts the MCU.
DMA Interrupt enable/disable bit. This bit is used to enable/disable the interrupt on transfer completion.
INE = 0
Interrupt is disabled. In addition, PPKT and TXFT do not clear the EN-bit and the DMAC is not disabled.
INE = 1
Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1 to 0 transition of the
EN bit. (When transfer is completed, EN = 0)
DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When the transfer completes, or when it
is terminated due to error, this bit is cleared. The 1 to 0 transition of this bit generates an interrupt (if interrupt is
enabled).
EN = 0
DMA is halted. The DMA is halted when the byte count reaches zero or transaction time-out occurs. When
halted, the DMA updates the byte count, sets NAK = 0 in OEDB, and interrupts the MCU (if INE = 1).
EN = 1
Setting this bit starts the DMA transfer.
4
XY
0
Next buffer to transmit/receive is the X buffer
5
CNT
0
6
INE
0
7
EN
0
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