參數(shù)資料
型號(hào)： TUSB3410VF
英文描述： BUS CONTROLLER
中文描述： 總線控制器
文件頁(yè)數(shù)： 45/92頁(yè)
文件大?。?/td> 317K
代理商： TUSB3410VF
6
–
5
6.1.4
DMACSR3: DMA Control And Status Register (UART Receive Channel) (Addr:FFE5)
This register is used to define the transaction time-out value. In addition, it contains a completion code that reports
any errors or a time-out condition.
7
6
5
4
3
2
1
0
TEN
C4
C3
C2
C1
C0
TXFT
OVRUN
R/W
R/W
R/W
R/W
R/W
R/W
R/C
R/C
BIT
0
NAME
OVRUN
RESET
0
FUNCTION
Overrun condition bit. This bit is set by DMA and cleared by the MCU (see Table 6
–
3)
OVRUN = 0
No overrun condition
OVRUN = 1
Overrun condition detected. When IEN = 0, this bit does not clear the EN bit in DMACDR;
therefore, the DMAC stays enabled, ready for the next transaction. Clears when the MCU writes
a 1. Writing a 0 has no effect.
Transfer time-out condition bit (see Table 6
–
3)
TXFT = 0
DMA stopped transfer without time-out
TXFT =1
DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear the EN bit in
DMACDR; therefore, the DMAC stays enabled, ready for the next transaction. Clears when the
MCU writes a 1. Writing a 0 has no effect.
This field is used to define the transaction time-out value in 1-ms increments. This value is loaded to a down
counter every time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the
counter decrements to zero it sets TXFT = 1 (in DMACSR register) and halts the DMA transfer. The counter starts
counting only when TEN = 1 and EN = 1 (in DMACDR
)
and the first byte has been received (see Figure 6
–
1).
00000 = 0-ms time-out
:
:
11111 = 31-ms time-out
Transaction time-out counter enable/disable bit
TEN = 0
TEN = 1
Counter is enabled
1
TXFT
0
6
–
2
C[4:0]
00000b
7
TEN
0
Counter is disabled (does not time-out)
Table 6
–
3. DMA IN-Termination Condition
IN TERMINATION
TXFT
OVRUN
COMMENTS
UART error
0
0
UART error condition detected
UART partial packet
1
0
This condition occurs when UART receiver has no more data for the host (data
starvation).
UART overrun
1
1
This condition occurs when X- and Y-input buffers are full and the UART FIFO is full (host
is busy).
6.2
Bulk Data I/O Using the EDB
The UBM (USB buffer manager) and the DMAC (DMA controller) access the EDB to fetch buffer parameters for IN
and OUT transactions (IN and OUT are with respect to host). In this discussion, it is assumed that (a) the MCU
initialized the EDBs, (b) DMA-continuous mode is being used, (c) double buffering is being used, and (d) the X/Y
toggle is controlled by the UBM.
NOTE:
The IN and OUT transfers apply to UART.
6.2.1
IN Transaction (TUSB3410 to Host)
1.
The MCU initializes the IEDB (64-byte packet, and double buffering is used) and the following DMA
registers:
DMACSR:
Defines the transaction time-out value.
DMACDR:
Defines the IEDB being used and the DMA mode of operation (continuous mode). Once this
register is set with EN = 1, the transfer starts.
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