參數(shù)資料
型號： TUSB3410VF
英文描述： BUS CONTROLLER
中文描述： 總線控制器
文件頁數(shù)： 43/92頁
文件大?。?/td> 317K
代理商： TUSB3410VF
6
–
3
6.1.2
DMACSR1: DMA Control And Status Register (UART Transmit Channel) (Addr:FFE1)
This register is used to define the transaction time-out value. In addition, it contains a completion code that reports
any errors or a time-out condition.
7
6
5
4
3
2
1
0
TEN
C4
C3
C2
C1
C0
TXFT
PPKT
R/W
R/W
R/W
R/W
R/W
R/W
R/C
R/C
BIT
0
NAME
PPKT
RESET
0
FUNCTION
Partial packet condition bit. This bit is set by the DMA and cleared by the MCU (see Table 6
–
2).
PPKT = 0
No partial-packet condition
PPKT = 1
Partial-packet condition detected. When IEN = 0, this bit does not clear the EN bit in DMACDR;
therefore, the DMAC stays enabled, ready for the next transaction. Clears when MCU writes a 1.
Writing a 0 has no effect.
1
TXFT
0
Transfer time-out condition (see Table 6
–
2)
TXFT = 0
DMA stopped transfer without time-out
TXFT = 1
DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear the EN bit in
DMACDR; therefore, the DMAC stays enabled, ready for the next transaction. DMA clears when
the MCU writes a 1. Writing a 0 has no effect.
6
–
2
C[4:0]
0
This field is used to define the transaction time-out value in 1-ms increments. This value is loaded to a down
counter every time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the
counter decrements to zero it sets TXFT = 1 (in DMACSR register) and halts the DMA transfer. The counter starts
counting only when TEN = 1 and EN = 1 (in DMACDR
)
and the first byte has been transmitted (see Figure 6
–
1).
00000 = 0-ms time-out
:
:
11111 = 31-ms time-out
7
TEN
0
Transaction time-out counter enable/disable bit.
TEN = 0
TEN = 1
Counter is disabled (does not time-out)
Counter is enabled
Table 6
–
2. DMA OUT-Termination Condition
OUT TERMINATION
TXFT
PPKT
COMMENTS
UART partial packet
0
1
This condition occurs when the host sends a partial packet.
UART time-out
1
0
This condition occurs when X- and Y-output buffers are full and the UART transmitter cannot
transmit (due to flow-control restriction) or if host has no data to transmit.
Counter
C[4:0]
TXFT
Load
SOF
TEN
EN
Figure 6
–
1. Transaction Time-Out Diagram
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