參數(shù)資料
型號(hào)： TSPC860SRMZPU50D4
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC PROCESSOR, PBGA357
封裝： PLASTIC, BGA-357
文件頁(yè)數(shù)： 69/90頁(yè)
文件大小： 2351K
代理商： TSPC860SRMZPU50D4
71
TSPC860
2129A–HIREL–08/02
Notes:
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1.
2. Also applies to CD and CTS hold time when they are used as an external sync signals.
SCC in NMSI Mode – Internal Clock Electrical Specifications
The electrical specifications in this document are preliminary.
Notes:
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1
2. Also applies to CD and CTS hold time when they are used as an external sync signals.
SCC In NMSI Mode – External Clock Electrical Specifications
The electrical specifications in this document are preliminary.
Num
Characteristic
All Frequencies
Unit
Min
Max
100
RCLK1 and TCLK1 Width High16
1/SYNCCLK
–
ns
101
RCLK1 and TCLK1 Width Low
1/SYNCCLK+5
–
ns
102
RCLK1 and TCLK1 Rise/Fall Time
–
15
ns
103
TXD1 Active Delay (From TCLK1 Falling Edge)
0
50
ns
104
RTS1 Active/Inactive Delay (From TCLK1 Falling Edge)
0
50
ns
105
CTS1 Setup Time to TCLK1 Rising Edge
5
–
ns
106
RXD1 Setup Time to RCLK1 Rising Edge
5
–
ns
107
RXD1 Hold Time from RCLK1 Rising Edge
5–
ns
108
CD1 Setup Time to RCLK1 Rising Edge
5
–
ns
Table 16. NMSI External Clock Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
100
RCLK1 and TCLK1
0
SYNCCLK/3
MHz
102
RCLK1 and TCLK1 Rise/Fall Time
–
ns
103
TXD1 Active Delay (From TCLK1 Falling Edge)
0
30
ns
104
RTS1 Active/Inactive Delay (From TCLK1 Falling Edge)
0
30
ns
105
CTS1 Setup Time to TCLK1 Rising Edge
40
–
ns
106
RXD1 Setup Time to RCLK1 Rising Edge
40
–
ns
107
RXD1 Hold Time from RCLK1 Rising Edge
0–
ns
108
CD1 Setup Time to RCLK1 Rising Edge
40
–
ns
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