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參數(shù)資料
| 型號(hào)： | TSPC860SRMZPU50D4 |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 50 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | PLASTIC, BGA-357 |
| 文件頁數(shù)： | 44/90頁 |
| 文件大?。?/td> | 2351K |
| 代理商： | TSPC860SRMZPU50D4 |
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49
TSPC860
2129A–HIREL–08/02
Figure 25. Asynchronous External Master Memory Access Timing (GPCM Controlled – ACS = ’00’)
Figure 26. Asynchronous External Master – Control Signals Negation Time
Notes:
1. The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level
sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the
CLKOUT.
2. The timings I41, I42 and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no direct
relation with the total system interrupt latency that the TSPC860 is able to support.
Figure 27. Interrupt Detection Timing for External Level Sensitive Lines
CLKOUT
AS
A[0:31],
TSIZ[0:1],
R/W
CSx
B39
B40
B22
AS
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
B43
Table 9. Interrupt Timing(2)
Num
Characteristic
All Frequencies
Unit
Min
Max
I39
IRQx Valid to CLKOUT Rising Edge (Set Up Time)
6
–
ns
I40
IRQx Hold Time After CLKOUT
2
–
ns
I41
IRQx Pulse Width Low
3
–
ns
I42
IRQx Pulse Width High
3
–
ns
I43
IRQx Edge to Edge Time
4XTCLOCKOUT
––
CLKOUT
IRQx
I39
I40
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