參數(shù)資料
型號(hào)： TSPC860SRMZPU50D4
廠商： E2V TECHNOLOGIES PLC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC PROCESSOR, PBGA357
封裝： PLASTIC, BGA-357
文件頁(yè)數(shù)： 35/90頁(yè)
文件大小： 2351K
代理商： TSPC860SRMZPU50D4
40
TSPC860
2129A–HIREL–08/02
Notes:
1. Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.
2. If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum values in
one cycle) or the frequency of the jitter is fast (i.e. it does not stay at an extreme value for a long time) then the maximum
allowed jitter on EXTAL can be up to 2%
3. The timings specified in B4 and B5 are based on full strength clock.
4. The timing for BR output is relevant when the PC860 is selected to work with the external bus arbiter. The timing for BG out-
put is relevant when the PC860 is selected to work with internal bus arbiter.
5. The timing required for BR input is relevant when the TSPC860 is selected to work with internal bus arbiter. The timing for
BG input is relevant when the TSPC860 is selected to work with internal bus arbiter.
6. The D (0:31) and DP (0:3) input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input signal is
asserted.
7. The D (0:31) and DP (0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for
read accesses controlled by chip-selects under control of the UPM in the Memory Controller, for data beats where DLT3 = 1
in the UPM RAM words. (This is only the cases where data is latched on the falling edge of CLKOUT).
8. The timing B30 refers to CS when ACS = 00 and to WE (0:3) when CSNT = 0
9. The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37
and B38 are specified to enable the freeze of the UPM output signals as described in Figure 22.
10. The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior speci-
fied in Figure 25.
Figure 8. External Clock Timing
B41
TS valid to CLKOUT Rising Edge (SetUp Time).
7
–
7
–
7
–
7
–
ns
B42
CLKOUT Rising Edge to TS Valid (Hold Time).
2
–
2
–
2
–
2
–
ns
B43
AS negation to Memory Controller Signals
Negation
–TBD
–
TBD
–TBD
ns
Table 8. Bus Operation Timings (Continued)
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
CLKOUT
B1
B5
B3
B4
B1
B2
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