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參數(shù)資料
| 型號： | TPS40180RGER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.05 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC24 |
| 封裝： | GREEN, PLASTIC, VQFN-24 |
| 文件頁數(shù)： | 32/52頁 |
| 文件大?。?/td> | 1291K |
| 代理商： | TPS40180RGER |
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www.ti.com
BOOT
Qg
C
55nF
V
=
D
(37)
SS
REF
I
T
C
22nF
V
=
(38)
Feedback Compensator Design
(
)
OUT
VC(s)
C
s
OUT
s C
ESR 1
R
1
G
DCR A
s
1
s C
R
1
+
=
t +
+
(39)
SLVS753B – FEBRUARY 2007 – REVISED NOVEMBER 2007
BP5
A 4.7-
resistor and 1-
F capacitor is placed between V
REG and BP5 as a low pass filter.
Phase Select (PSEL)
If the board is configured as a clock master for a multiphase application, an 8-phase CLKIO signal is generated if
PSEL pin is open, and a 6-phase CLKIO signal is generated if PSEL is tied to ground with a 29.4-k
resistor. If
the board is stacked as a slave for a multiphase application, a different resistor value is selected. The PSEL
resistor selection is illustrated in the previous datasheet section.
VSHARE (VSH)
A 1-
F capacitor is tied from VSHARE to GND.
Powergood (PGOOD)
The PGOOD pin is tied to BP5 with a 10-k
resistor.
Undervoltage Lockout (UVLO)
UVLO is connected to the input voltage with a resistor divider. The two resistors have the same value of 10 k
.
When the input voltage is higher than 2 V, the internal linear regulator is enabled.
Clock Synchronization (CLKIO)
CLKIO is floating as no clock synchronization required for single output configuration.
Bootstrap Capacitor
A bootstrap capacitor is connected between the BOOT and SW pin. The bootstrap capacitor depends on the
total gate charge of the high side MOSFET and the amount of droop allowed on the bootstrap capacitor
Qg is 11 nC and is 0.2 V in the calculation. For this application, a 0.1-
F capacitor is selected.
Soft-Start (SS)
To get about 1-ms soft-start time, a 22-nF capacitor is tied to SS pin.
ISS is the soft-start current which is 15- A typically. VREF is the reference voltage 0.7 V.
Remote Sense
VOUT and GSNS are connected to the remote sensing output connector. DIFFO is connected to the output
voltage setting resistor divider. If the differential amplifier is not used, VOUT and GSNS are suggested to be
grounded, and DIFFO is left open.
Peak current mode control method is employed in the controller. A small signal model is developed from the
COMP signal to the output.
The time constant is defined by:
38
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40180
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