參數(shù)資料
型號： TPS40180RGER
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 0.05 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC24
封裝： GREEN, PLASTIC, VQFN-24
文件頁數(shù)： 22/52頁
文件大?。?/td> 1291K
代理商： TPS40180RGER
www.ti.com
SLVS753B – FEBRUARY 2007 – REVISED NOVEMBER 2007
The 10-k
resistor connected from the CLKIO line to GND is required to ensure that the CLKIO line falls to GND
quickly when the master device is shutdown or powers off. The master CLKIO pin goes to a high impedance
state at these times and if the CLKIO line was high, there is no other active discharge part. The slave controllers
look at the CLKIO line to determine if the system is supposed to be running or not. A level below 0.5V on CLKIO
is required for this purpose. If the CLKIO line remains high after that master is shut down, the slaves continue to
operate. This is seen as the slave LDRV signal remaining high for a period of time after the master is shut down
and results in output voltage excursions that are not controlled.
NOTE:
In any system configured to have a CLK master and CLK slaves, a 10-k
resistor
connected from CLKIO to GND is required.
For simplicity of design, the compensation components shown on the master, as well as the components
connected to the RT and SS pins may be present on the slaves. This prevents separate designs being
necessary for master and slave circuits. The RT and SS pins can have jumper option to tie them to VDD to
program an individual device as a slave. These components were omitted in Figure 31.
Selection of the PSEL pin resistors is simple. First determine if the master should generate a CLK signal that is
suitable for 60 or 45 spacing of the phases. Select the appropriate PSEL connection option from Table 3. For the
slaves, determine the desired firing angle for each one and pick the appropriate resistor from either Table 4 or
Table 5 depending on the clock scheme chosen for the master.
Design Note: When used in a master/slave relationship and an overvoltage event occurs, only the control loop
master turns on the low-side FET to pull down the output voltage. This results in the master phase low-side FET
sinking all of the combined maximum current for the slaves. For example, if the per phase current limit is 10 A
and there are 4 phases, the master low-side FET could be required to pass 30 A for a brief time. The master
error amplifier is still active during this time and tries to have the slaves regulate the output voltage. As the
master COMP pin rises to the ILIM point, a fault event is sensed and the converter shuts down, and then initiate
a hiccup restart. Size the master low-side FET to handle the appropriate amount of surge current for 7 clock
cycles of the converter.
Copyright 2007, Texas Instruments Incorporated
29
Product Folder Link(s): TPS40180
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TPS40180RGET 功能描述:DC/DC 開關(guān)控制器 Single Ph Stackable Controller RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK
TPS40180RGETG4 功能描述:DC/DC 開關(guān)控制器 Sgl Phase Stackable Cntrlr RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK
TPS40190 制造商:TI 制造商全稱:Texas Instruments 功能描述:LOW PIN COUNT SYNCHRONOUS BUCK CONTROLLER
TPS40190DRC 制造商:Texas Instruments 功能描述:DC/DC CONTROLLER
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