參數(shù)資料
型號(hào): TPS28225DT
廠(chǎng)商: Texas Instruments, Inc.
英文描述: High-Frequency 4-A Sink Synchronous MOSFET Driver
中文描述: 高頻率的4 - A水槽同步MOSFET驅(qū)動(dòng)器
文件頁(yè)數(shù): 8/30頁(yè)
文件大小: 951K
代理商: TPS28225DT
www.ti.com
Normal switching
PWM
LGATE
UGATE
3 State
window
90 %
10 %
tDLL
50 %
tFL
50 %
tPWM_MIN
tDTU
90 %
10 %
tRU
90 %
10 %
tDLU
tFU
tDTL
90 %
10 %
tRL
tHLD_R
90 %
10 %
90 %
90 %
tHLD_F
Enter into
3 State
at PWM rise
Exit
3 State
Enter into
3 State
at PWM fall
PWM Low and High after
State to allow Bootstrap
Capacitor Restore Charge
3
TRUTH TABLE
TPS28225
SLUS710–MAY 2006
TERMINAL FUNCTIONS
TERMINAL
DRB-8
1
I/O
DESCRIPTION
SOIC-8
1
NAME
UGATE
O
Upper gate drive sink/source output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between
this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper
MOSFET.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states
during operation, see the 3-state PWM Input section under DETAILED DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
Ground pin. All signals are referenced to this node.
2
2
BOOT
I/O
3
3
PWM
I
4
4
GND
Thermal
pad
Exposed
die pad
Connect directly to the GND for better thermal performance and EMI
Lower gate drive sink/source output. Connect to the gate of the low-side power N-Channel
MOSFET.
Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor from this pin to GND.
Enable/Power Good input/output pin with 1M
impedance. Connect this pin to HIGH to enable
and LOW to disable the IC. When disabled, the device draws less than 350
μ
A bias current. If the
V
is below UVLO threshold or over temperature shutdown occurs, this pin is internally pulled
low.
Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin
provides a return path for the upper gate driver.
5
5
LGATE
O
6
6
VDD
I
7
7
EN/PG
I/O
8
8
PHASE
I
TIMING DIAGRAM
V
DD
FALLING > 3 V AND T
J
< 150
°
C
EN/PG FALLING > 1.0 V
PWM > 1.5 V AND
PWM < 1 V
T
RISE
/T
FALL
< 200 ns
High
Low
Low
High
V
DD
RISING < 3.5 V
OR T
J
> 160
°
C
PIN
EN/PG RISING
< 1.7 V
PWM SIGNAL SOURCE IMPEDANCE
>40 k
FOR > 250ns (3-State)
(1)
Low
Low
LGATE
UGATE
EN/PG
Low
Low
Low
Low
Low
(1)
To exit the 3-state condition, the PWM signal should go low. One Low PWM input signal followed by one High PWM input signal is
required before re-entering the 3-state condition.
8
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