參數(shù)資料
型號: TPS28225DT
廠商: Texas Instruments, Inc.
英文描述: High-Frequency 4-A Sink Synchronous MOSFET Driver
中文描述: 高頻率的4 - A水槽同步MOSFET驅(qū)動器
文件頁數(shù): 15/30頁
文件大?。?/td> 951K
代理商: TPS28225DT
www.ti.com
3-STATE INPUT
As soon as the EN/PG pin is set high and input PWM pulses are initiated (see 1 below
(1)
). The dead-time control
circuit ensures that there is no overlapping between UGATE and LGATE drive outputs to eliminate shoot
through current through the external power FETs. Additionally to operate under periodical pulse sequencing, the
TPS28225 has a self-adjustable PWM 3-state input circuit. The 3-state circuit sets both gate drive outputs low,
and thus turns the external power FETs OFF if the input signal is in a high impedance state for at least 250 ns
typical. At this condition, the PWM input voltage level is defined by the internal 27k
to 13k
resistor divider
shown in the block diagram. This resistor divider forces the input voltage to move into the 3-state window.
Initially the 3-state window is set between 1.0-V and 2.0-V thresholds. The lower threshold of the 3-state window
is always fixed at about 1.0 V. The higher threshold is adjusted to about 75% of the input signal amplitude. The
self-adjustable upper threshold allows shorter delay if the input signal enters the 3-state window while the input
signal was high, thus keeping the high-side power FET in ON state just slightly longer then 250 ns time constant
set by an internal 3-state timer. Both modes of operation, PWM input pulse sequencing and at the 3-state
condition, are illustrated in the timing diagrams shown in
Figure 18
. The self-adjustable upper threshold allows
operation in wide range amplitude of input PWM pulse signals. The waveforms in
Figure 20
and
Figure 21
illustrate operation at normal and 3-state mode with the input pulse amplitudes 6 V and 2.5 V accordingly. After
entering into the 3-state window and staying within the window for the hold-off time, the PWM input signal level
is defined by the internal resistor divider and, depending on the input pulse amplitude, can be pulled up above
the normal PWM pulse amplitude (
Figure 21
) or down below the normal input PWM pulse (
Figure 20
). To exit
from the 3-state operation mode, the input signal should go low and then high at least once. This is necessary to
restore the voltage across the bootstrap capacitor that could be discharged during the 3-state mode if the 3-state
condition lasts long enough.
TPS28225
SLUS710–MAY 2006
DETAILED DESCRIPTION (continued)
The EN/PG pin can serve as the second pulse input of the driver additionally to PWM input. The delay between
EN/PG and the UGATE going high, provided that PWM input is also high, is only about 30ns. If the PWM input
pulses are synchronized with EN/PG input, then when PWM and EN/PG are high, the UGATE is high and
LGATE is low. If both PWM and EN/PG are low, then UGATE and LGATE are both low as well. This means the
driver allows operation of a synchronous buck regulator as a convertional buck regulator using the body diode of
the low side power MOSFET as the freewheeling diode. This feature can be useful in some specific applications
to allow startup with a pre-biased output or, to improve the efficiency of buck regulator when in power saving
mode with low output current.
Figure 20. 6-V Amplitude PWM Pulse
Figure 21. 2.5-V Amplitude PWM Pulse
(1)
The driver sets UGATE low and LGATE high when PWM is low. When the PWM goes high, UGATE goes high and LGATE goes low.
15
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