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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點(diǎn)DSP) |
| 中文描述： | 定點(diǎn)數(shù)字信號處理器（定點(diǎn)DSP）的 |
| 文件頁數(shù)： | 8/35頁 |
| 文件大?。?/td> | 443K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
NAME
DESCRIPTION
I/O
TERMINAL
HOST PORT INTERFACE SIGNALS (CONTINUED)
HCNTL0
HCNTL1
I
Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have internal
pullup resistors that are only enabled when HPIENA = 0.
HBIL
I
Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup resistor
that is only enabled when HPIENA = 0.
HCS
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input has
an internal pullup resistor that is only enabled when HPIENA = 0.
HDS1
HDS2
I
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs
have internal pullup resistors that are only enabled when HPIENA = 0.
HAS
I
Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA register.
HAS has an internal pullup resistor that is only enabled when HPIENA = 0.
HR/W
I
Read/write. HR/W controls the direction of an HPI transfer. R/W has an internal pullup resistor that is only enabled
when HPIENA = 0.
HRDY
O/Z
Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the
high-impedance state when OFF is low.
Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high
.
The signal goes
into the high-impedance state when OFF is low.
HINT
O/Z
HPIENA
I
HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor is always
active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low during reset,
the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the ’UVC5409 is reset.
HPI16
I
HPI 16-bit select pin. HPI16 = 1 selects the non-multiplexed mode. The non-multiplexed mode allows hosts with sepa-
rate address/data buses to access the HPI address range via the 16 address pins (A0–A15). The 16-bit data is also
accessible through pins D0 through D15. Host-to-DSP and DSP-to-Host interrupts are not supported. There are no
HPIC and HPIA registers in the non-multiplexed mode since HCNTRL0 and HCNTRL1 signals are available.
SUPPLY PNS
CVDD
DVDD
VSS
S
+VDD. Dedicated 1.8-V power supply for the core CPU
+VDD. Dedicated 3.3-V power supply for the I/O pins
Ground
S
S
TEST PINS
TCK
I
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,
or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling
edge of TCK.
TDI
I
IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of
TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress.
TDO also goes into the high-impedance state when OFF is low.
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the
TAP controller on the rising edge of TCK.
TRST
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
I = Input, O = Output, Z = High-impedance, S = Supply
A
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