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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點DSP) |
| 中文描述： | 定點數(shù)字信號處理器（定點DSP）的 |
| 文件頁數(shù)： | 24/35頁 |
| 文件大?。?/td> | 443K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
DMA channel interrupt selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the
number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.
DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When
the ’UVC5409 is reset, the interrupts from these three DMA channels are deselected. The INTSEL bit field in
the DMPREC register can be used to select these interrupts, as shown in Table 8.
Table 8. DMA Channel Interrupt Selection
INTSEL Value
IMR/IFR[6]
IMR/IFR[7]
IMR/IFR[10]
IMR/IFR[11]
00b (reset)
BRINT2
BXINT2
BRINT1
BXINT1
01b
BRINT2
BXINT2
DMAC2
DMAC3
10b
DMAC0
DMAC1
DMAC2
DMAC3
11b
Reserved
memory-mapped registers
The ’UVC5409 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses
0h to 1Fh. The device also has a set of memory-mapped registers associated with peripherals. Table 9 gives
a list of CPU memory-mapped registers (MMRs) available on ’UVC5409. Table 10 shows additional peripheral
MMRs associated with the ’UVC5409.
A
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