參數(shù)資料
型號(hào)： TMS320UVC5409
廠商： Texas Instruments, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor(定點(diǎn)DSP)
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器（定點(diǎn)DSP）的
文件頁(yè)數(shù)： 17/35頁(yè)
文件大?。?/td> 443K
代理商： TMS320UVC5409
TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
enhanced 8-bit host-port interface (HPI8/16) (continued)
0000h
005Fh
Reserved
0060h
007Fh
0080h
Scratch-Pad
RAM
7FFFh
8000h
On-Chip RAM
(32K x 16 Bits)
FFFFh
Reserved
Figure 6. ’UVC5409 HPI Memory Map
multichannel buffered serial ports
The ’UVC5409 device has three high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow
direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based
on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides:
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
Direct interface to:
–
T1/E1 framers
–
MVIP switching-compatible and ST-BUS compliant devices
–
IOM-2 compliant devices
–
AC97-compliant devices
–
Serial peripheral interface (SPI ) devices
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
μ
-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
BCLKX
BDX
BFSX
BCLKR
BDR
BFSR
Transmit reference clock
Transmit data
Transmit frame synchronization
Receive reference clock
Receive data
Receive frame synchronization
A
SPI is a trademark of Motorola Inc.
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