參數(shù)資料
型號(hào)： TMS320UVC5409
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor(定點(diǎn)DSP)
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器（定點(diǎn)DSP）的
文件頁(yè)數(shù)： 19/35頁(yè)
文件大?。?/td> 443K
代理商： TMS320UVC5409
TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock generator
The clock generator provides clocks to the ’UVC5409 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock
input is then divided by two (DIV mode) to generate clocks for the ’UVC5409 device, or the PLL circuit can be
used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor,
allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that,
once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the
’UVC5409 device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of
the ’UVC5409 to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in
software-programmable PLL can be configured in one of two clock modes:
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be
completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon
reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the
CLKMD1 – CLKMD3 pins as shown in Table 5.
Table 5. Clock Mode Settings at Reset
CLKMD1
CLKMD2
CLKMD3
CLKMD
RESET VALUE
CLOCK MODE
0
0
0
E007h
PLL x 15
0
0
1
9007h
PLL x 10
0
1
0
4007h
PLL x 5
1
0
0
1007h
PLL x 2
1
1
0
F007h
PLL x 1
1
1
1
0000h
1/2 (PLL disabled)
1
0
1
F000h
1/4 (PLL disabled)
0
1
1
—
Reserved (Bypass mode)
A
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