參數(shù)資料
型號(hào)： TMS320UVC5409
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor(定點(diǎn)DSP)
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器（定點(diǎn)DSP）的
文件頁(yè)數(shù)： 27/35頁(yè)
文件大?。?/td> 443K
代理商： TMS320UVC5409
TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
27
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
McBSP control registers and subaddresses
The control registers for the multi-channel buffered serial port (McBSP) are accessed using the sub-bank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location.
The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the
subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected register.
Table 11 shows the McBSP control registers and their corresponding subaddresses.
Table 11. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
NAME
ADDRESS
NAME
ADDRESS
SUB
ADDRESS
DESCRIPTION
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
MCR10
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
DMA sub-bank addressed registers
SPCR10
39h
39h
MCR11
SPCR11
49h
49h
08h
00h
Multichannel register 1
Serial port control register 1
SPCR20
39h
SPCR21
49h
01h
Serial port control register 2
ááááááááááááááááááááááááááááááá
SRGR20
MCR20
39h
39h
SRGR21
MCR21
49h
49h
07h
09h
Sample rate generator register 2
Multichannel register 2
ááááááááááááááááááááááááááááááá
RCERA0
39h
RCERA1
49h
0Ah
Receive channel enable register partition A
ááááááááááááááááááááááááááááááá
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set, or sub-bank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register
within the sub-bank, while the DMA subbank data (DMSDN) register or the DMA sub-bank data register with
auto-increment (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincremented so that a subsequent access affects the next register within the sub-bank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the auto-increment feature
is not required, the DMSDN register should be used to access the subbank. Table 12 shows the DMA controller
subbank addressed registers and their corresponding subaddresses.
A
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