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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點DSP) |
| 中文描述： | 定點數(shù)字信號處理器（定點DSP）的 |
| 文件頁數(shù)： | 15/35頁 |
| 文件大小： | 443K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
programmable bank-switching wait states
The programmable bank-switching logic of the ’UVC5409 is functionally equivalent to that of the ’548/’549
devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within
program or data memory space. A bank-switching wait state can also be automatically inserted when accesses
cross the data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait-states. Figure 5
shows the BSCR and its bits are described in Table 4.
BNKCMP
PS-DS
Reserved
HBH
12
11
3
2
1
15
R/W-0
R-0
R/W-1
R/W-1111
(R = Read, W = Write)
BH
EXIO
0
10
R/W-0
R/W-0
Figure 5. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
Table 4. Bank-Switching Control Register Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
15–12
BNKCMP
1111
Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four
MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared,
resulting in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
11
PS - DS
1
Program read – data read access. PS-DS inserts an extra cycle between consecutive accesses of
program read and data read or data read and program read.
PS-DS = 0
No extra cycles are inserted by this feature.
PS-DS = 1
One extra cycle is inserted between consecutive data and program reads.
10–3
Reserved
0
These bits are reserved and are unaffected by writes.
HPI bus holder. HBH controls the HPI bus holder feature. HBH is cleared to 0 at reset
.
HBH = 0
The bus holder is disabled.
HBH = 1
The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the
previous logic level.
2
HBH
0
1
BH
0
Bus holder. BH controls the data bus holder feature. BH is cleared to 0 at reset.
BH = 0
The bus holder is disabled.
BH = 1
The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the
previous logic level.
External bus interface off. The EXIO bit controls the external bus-off function.
EXIO = 0
The external bus interface functions as usual.
EXIO = 1
The address bus, data bus, and control signals become inactive after completing the
current bus cycle Note that the DROM MP/MC and OVLY bits in the PMST and the HM
current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM
bit of ST1 cannot be modified when the interface is disabled.
0
EXIO
0
A
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