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參數(shù)資料
| 型號： | TMS320UVC5402 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點DSP) |
| 中文描述： | 定點數(shù)字信號處理器（定點DSP）的 |
| 文件頁數(shù)： | 8/60頁 |
| 文件大小： | 772K |
| 代理商： | TMS320UVC5402 |
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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
NAME
DESCRIPTION
TYPE
TERMINAL
HOST-PORT INTERFACE SIGNALS (CONTINUED)
HR/W
I
Read/write. HR/W controls the direction of an HPI transfer. HR/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
HRDY
O/Z
Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the
high-impedance state when EMU1/OFF is low.
Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high
.
HINT can also
be configured as the timer 1 output (TOUT1) when the HPI is disabled. The signal goes into the high-impedance
state when EMU1/OFF is low.
HINT
O/Z
HPIENA
I
HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor
is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low
during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the
’UVC5402 is reset.
SUPPLY PNS
CVDD
DVDD
VSS
S
+VDD. Dedicated power supply for the core CPU
+VDD. Dedicated power supply for the I/O pins
Ground
S
S
TEST PINS
TCK
I
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction
register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
on the falling edge of TCK.
TDI
I
IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when EMU1/OFF is low.
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TRST
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode,
and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
EMU0
I/O/Z
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by
way of the IEEE standard 1149.1 scan system.
EMU1/OFF
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST
is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers
into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Therefore, for the OFF feature, the following apply:
TRST = low
EMU0 = high
EMU1/OFF = low
I = input, O = output, Z = high impedance, S = supply
P
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