參數(shù)資料
型號(hào)： TMS320UVC5402
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor(定點(diǎn)DSP)
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器（定點(diǎn)DSP）的
文件頁(yè)數(shù)： 18/60頁(yè)
文件大?。?/td> 772K
代理商： TMS320UVC5402
TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock generator (continued)
Unlike previous ’54x products, the ’UVC5402 does not include an on-chip oscillator or phased-locked loop (PLL)
circuit.
The clock option is selected using the 16-bit memory-mapped (address 0058h) clock mode (CLKMD) register.
Upon reset, the CLKMD register is initialized to one of the three clock options dependent on the state of the clock
mode select pins (CLKMD1 – CLKMD3). The clock mode select pins are latched while the reset pin is low and
the clock generator is configured in the selected mode. The clock mode select pin combinations and
corresponding clock modes are listed in Table 5.
Table 5. Clock Mode Settings at Reset
CLKMD1
CLKMD2
CLKMD3
CLKMD
RESET VALUE
0F01h
CLOCK MODE
0
1
1
1/1 (bypass)
1
1
1
0000h
1/2
1
0
1
F000h
1/4
0
0
0
—
Reserved
0
0
1
—
Reserved
0
1
0
—
Reserved
1
0
0
—
Reserved
1
1
0
—
Reserved
The state of the clock mode select pins should not be changed while the reset pin is high. Following reset, the
clock mode can be changed through software by writing to the CLKMD register. Only the three values listed in
the CLKMD RESET VALUE column of Table 5 can be written to the clock mode register and no other bit
combinations are allowed.
DMA controller
The ’UVC5402 direct memory access (DMA) controller transfers data between points in the memory map
without intervention by the CPU. The DMA controller allows movements of data to and from internal
program/data memory or internal peripherals (such as the McBSPs) to occur in the background of CPU
operation. The DMA has six independent programmable channels, allowing six different contexts for DMA
operation.
features
The DMA has the following features:
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for internal accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be postincremented,
postdecremented, or be adjusted by a programmable value.
Each read or write transfer may be initialized by selected events.
Upon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to the
CPU.
The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).
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