參數(shù)資料
型號(hào)： TMS320UVC5402
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor(定點(diǎn)DSP)
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器（定點(diǎn)DSP）的
文件頁(yè)數(shù)： 38/60頁(yè)
文件大?。?/td> 772K
代理商： TMS320UVC5402
TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
ready timing for externally generated wait states
timing requirements for externally generated wait states [H = 0.5 t
c(CO)
]
(see Figure 13, Figure 14,
Figure 15, and Figure 16)
MIN
MAX
UNIT
tsu(RDY)
th(RDY)
tv(RDY)MSTRB
th(RDY)MSTRB
tv(RDY)IOSTRB
th(RDY)IOSTRB
tv(MSCL)
tv(MSCH)
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Setup time, READY before CLKOUT low
10
ns
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low
Hold time, READY after MSTRB low
Valid time, READY after IOSTRB low
Hold time, READY after IOSTRB low
0
ns
4H–15
ns
4H
ns
5H–15
ns
5H
ns
Valid time, MSC low after CLKOUT low
0
8
ns
Valid time, MSC high after CLKOUT low
0
8
ns
MSC
MSTRB
READY
A[19:0]
CLKOUT
tv(MSCH)
tv(MSCL)
th(RDY)
th(RDY)MSTRB
tv(RDY)MSTRB
Wait State
Generated
by READY
Wait States
Generated Internally
tsu(RDY)
Figure 13. Memory Read With Externally Generated Wait States
P
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