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參數(shù)資料
| 型號： | TMS320UVC5402 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點DSP) |
| 中文描述： | 定點數(shù)字信號處理器（定點DSP）的 |
| 文件頁數(shù)： | 16/60頁 |
| 文件大?。?/td> | 772K |
| 代理商： | TMS320UVC5402 |
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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial ports
The ’UVC5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that
allow direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are
based on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP
provides:
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
Direct interface to:
–
T1/E1 framers
–
MVIP switching compatible and ST-BUS compliant devices
–
IOM-2 compliant devices
–
Serial peripheral interface devices
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
μ
-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
BCLKX
BDX
BFSX
BCLKR
BDR
BFSR
Transmit reference clock
Transmit data
Transmit frame synchronization
Receive reference clock
Receive data
Receive frame synchronization
The six pins listed are functionally equivalent to the pins of previous serial port interface pins in the ’C5000 family
of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX
pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register
(DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure
allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.
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