參數(shù)資料
型號(hào)： TMS320F206PZA
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 25/57頁(yè)
文件大?。?/td> 793K
代理商： TMS320F206PZA
TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
25
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multiprocessing
The flexibility of the ’C20x allows configurations to satisfy a wide range of system requirements; the device can
be used in a variety of system configurations, including but not limited to the following:
A standalone processor
A multiprocessor with devices in parallel
A slave/host multiprocessor with global memory space
A peripheral processor interfaced to another device via the processor-controlled signals
For multiprocessing applications, the ’F206 has the capability of allocating global memory space and
communicating with that space by way of the BR and READY control signals. Global memory is data memory
shared by more than one device. Global memory accesses must be arbitrated. The 8-bit memory-mapped
global memory allocation register (GREG) specifies part of the ’C20x’s data memory as global external memory.
The contents of the register determine the size of the global memory space. If the current instruction addresses
an operand within that space, BR is asserted to request control of the bus. The length of the memory cycle is
controlled by the READY line.
The TMS320F206 supports direct memory access (DMA) to its local (off-chip) program, data, and I/O spaces.
Two signals, HOLD/INT1, an input to the device, and HOLDA, an output, control this mechanism. The Hold
feature is enabled by clearing the mode bit in the interrupt control register (ICR IS@FFECh). When the Hold
feature is enabled, and HOLD/INT1 is asserted, executing an IDLE instruction puts the address, data, and
memory control signals (PS, DS, IS, STRB, R/W, and WE) in a high-impedance state. When this occurs, the
HOLDA signal is asserted, acknowledging that the processor has relinquished control of the external bus. It is
important to note that when the mode bit is set to one, the Hold feature is disabled, and the HOLD/INT1 pin
functions as a general-purpose interrupt (INT1). That is, when the Hold feature is disabled, and HOLD/INT1 is
asserted, the IDLE instruction does not cause the memory interface signals to enter the high-impedance mode,
and it does not cause the assertion of HOLDA. At reset, the mode bit is cleared to zero, and the Hold feature
is enabled.
instruction set
The ’C20x microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control. Source code for the ’C1x and ’C2x DSPs is upwardly compatible with the ’C20x.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies depending upon whether the next data operand fetch is from internal or
external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.
addressing modes
The ’C20x instruction set provides four basic memory-addressing modes: direct, indirect, immediate, and
register.
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.
Thus, in the direct-addressing mode, data memory is effectively paged with a total of 512 pages, each page
containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0–AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
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