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| 型號： | TMS320F206PZA |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 21/57頁 |
| 文件大小： | 793K |
| 代理商： | TMS320F206PZA |
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TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external interface (continued)
I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O
address space using the processor’s external address and data buses in the same manner as memory-mapped
devices.
The ’F206 external parallel interface provides various control signals to facilitate interfacing to the device. The
R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal
provides a timing reference for all external cycles. For convenience, the device also provides the RD and the
WE output signals, which indicate a read and a write cycle, respectively, along with timing information for those
cycles. The RD pin provides additional flexibility through software control. The RD pin can be configured to
provide an inverted R/W signal instead of the standard RD signal. The FRDN bit (bit 15) of the PMST register
controls the RD pin signal selection. For more details on the FRDN bit control selection, see the PMST register
description in Table 8. The availability of these signals minimizes external gating necessary for interfacing
external devices to the ’F206.
The bus request (BR) signal is used in conjunction with the other ’F206 interface signals to arbitrate external
global memory accesses. Global memory is external data memory space in which the BR signal is asserted at
the beginning of the access. When an external global memory device receives the bus request, it responds by
asserting the READY signal after the global memory access is arbitrated and the global access is completed.
The TMS320F206 supports zero-wait-state reads on the external interface. However, to avoid bus conflicts,
writes take two cycles. This allows the TMS320F206 to buffer the transition of the data bus from input to output
(or output to input) by a half cycle. In most systems, TMS320F206 ratio of reads to writes is significantly large
to minimize the overhead of the extra cycle on writes.
Wait states can be generated when accessing slower external resources. The wait states operate on
machine-cycle boundaries and are initiated either by using the READY pin or using the software wait-state
generator. The READY pin can be used to generate any number of wait states. When using the READY pin to
communicate with slower devices, the ’F206 processor waits until the slower device completes its function and
signals the processor by way of the READY line. Once a ready indication is provided back to the ’F206 from
the external device, execution continues. For external wait states using the READY pin, the on-chip wait-state
generator should be programmed to generate at least one wait state.
interrupts and subroutines
The ’F206 implements three general-purpose interrupts, INT3–INT1, along with reset (RS) and the
nonmaskable interrupt (NMI) which are available for external devices to request the attention of the processor.
Internal interrupts are generated by: the serial port (RINT and XINT), the timer (TINT), the UART, the TXRXINT
bit in the IMR, and by the software-interrupt instructions (TRAP, INTR and NMI). Interrupts are prioritized with
RS having the highest priority, followed by NMI, and timer or UART having the lowest priority. Additionally, any
interrupt except RS and NMI can be individually masked with a dedicated bit in the interrupt mask register (IMR)
and can be cleared, set, or tested using its own dedicated bit in the interrupt flag register (IFR). The reset and
NMI functions are not maskable.
All interrupt vector locations are on two-word boundaries so that branch instructions can be accommodated in
those locations if desired.
A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle
instruction, the interrupt is not processed until the instruction completes execution. This mechanism applies to
instructions that are repeated (using the RPT instruction) and to instructions that become multicycle because
of wait states.
Each time an interrupt is serviced or a subroutine is entered, the PC is pushed onto an internal hardware stack,
providing a mechanism for returning to the previous context. The stack contains eight locations, allowing
interrupts or subroutines to be nested up to eight levels deep.
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