參數(shù)資料
型號(hào)： TMS320F206PZA
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 24/57頁(yè)
文件大小： 793K
代理商： TMS320F206PZA
TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
input clock options
The TMS320F206 provides multiple clock modes of divide-by-two and multiply-by-one, -two, or -four. The clock
mode configuration cannot be dynamically changed without executing another reset.
synchronous serial port
A full-duplex (bidirectional) 16-bit on-chip synchronous serial port provides direct communication with serial
devices such as codecs, serial A/D (analog-to-digital) converters, and other serial systems. The interface
signals are compatible with codecs and many other serial devices. The serial port can also be used for
intercommunication between processors in multiprocessing applications.
For data transmission, three signals are necessary to connect the transmit pins of the transmitting device with
the receive pins of the receiving device. The transmitted serial data signal (DX) sends the actual data. The
transmit frame synchronization signal (FSX) initiates the transfer (at the beginning of the packet), and the
transmit clock signal (CLKX) clocks the bit transfer. The corresponding pins on the receive interface are DR,
FSR and CLKR, respectively. When the serial port is not used, the device can be configured to shut off the serial
port internal clocks, allowing the device to run in a lower power mode of operation.
The continuous mode of the synchronous serial port (SSP) provides operation that, once initiated, requires no
further frame synchronization pulses when transmitting at maximum packet frequency. Both receive and
transmit operations have a four-deep first-in-first-out (FIFO) buffer. The advantage of having a FIFO is to
alleviate the CPU from being loaded with the task of servicing a receive- or transmit-data operation after each
word, allowing a continuous communications stream of 16-bit data packets. The maximum transfer rate for both
transmit and receive operations is CLKOUT1(frequency)/2. Therefore, the maximum rate at 20 million
instructions per second (MIPS) is 10 megabits per second (Mbps). The serial port is fully static and functions
at arbitrarily low clocking frequencies.
enhanced synchronous serial port features
The synchronous serial port of the TMS320F206 device is an enhanced synchronous serial port (ESSP). The
ESSP features facilitate a glueless interface with multiple codecs and other peripherals. The SSP registers are
complemented with three additional registers—ESSP status register (SSPST), ESSP multichannel register
(SSPMC), and ESSP counter register (SSPCT)—to define the ESSP features. The SSPST includes control and
status bits for some of the new ESSP features. Additional control bits are provided in the SSPMC to control the
multichannel and prescaled clocks/frames features. The SSPCT register contains the two 8-bit prescalers to
provide variable synchronous shift clock (CLKX) and frame syncs (FSX).
asynchronous serial port
The asynchronous serial port is full-duplexed and transmits and receives 8-bit data. For transmit and receive
data there is one start bit and one or two configurable stop bits by way of the asynchronous serial port control
register (ASPCR). Double-buffering of transmit/receive data is used in all modes. Baud-rate generation is
accomplished by way of the baud-rate divisor register (BRD). This port also features auto-baud-detection logic.
scan-based emulation
TMS320F206 devices incorporate scan-based emulation logic for code- and hardware-development support.
Scan-based emulation allows the emulator to control the processor in the system without the use of intrusive
cables to the full pinout of the device. The scan-based emulator communicates with the ’F206 by way of the
IEEE 1149.1 (JTAG) interface.
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